Re: [PATCH v3 0/3] mtd: rawnand: sunxi: fix H6/H616 controller timings
Miquel Raynal <[email protected]>
| Newsgroups | dev.linux.lists.linux-sunxi,org.infradead.lists.linux-arm-kernel,org.infradead.lists.linux-mtd,org.kernel.vger.linux-kernel,org.kernel.vger.stable |
|---|---|
| Message-ID | <[email protected]> |
On Fri, 07 Aug 2026 09:38:58 -0600, James Hilliard wrote:
> The sunxi NAND timing solver currently applies the original A10 NDFC
> timing characteristics to every supported controller. The H6/H616 NDFC
> uses two internal cycles for several setup and hold intervals and has
> different delay-field encodings, so the resulting clock and timing
> register values do not match the hardware.
>
> Prepare for per-controller timing data in two behaviorally focused
> patches, then add and select the H616 characteristics in the final fix.
> Legacy controllers retain their existing setup-cycle behavior and delay
> encodings.
>
> [...]
Applied to nand/next, thanks!
[1/3] mtd: rawnand: sunxi: group controller delay tables
commit: 9f2e033754c6c023150f184b4e72bbcc5d6eea13
[2/3] mtd: rawnand: sunxi: describe tADL and tWHR delays
commit: 147f2a5743f8864bfc265654b1856af11c8c0031
[3/3] mtd: rawnand: sunxi: fix H6/H616 controller timings
commit: 15a3cbce32994141252bb4ecfe3ff3a5d22d0b4f
Patche(s) should be available on mtd/linux.git and will be
part of the next PR (provided that no robot complains by then).
Kind regards,
Miquèl