[PATCH v2] phy: allwinner: sun4i-usb: disable the PHY2 PMU clock after SIDDQ setup

From: Xu Rao <[email protected]>

sun4i_usb_phy_init() temporarily enables PHY2's clk2 when a SoC needs
PHY2 SIDDQ setup while initializing another PHY. However, after updating
PHY2's PMU register it disables the clk2 pointer from the PHY currently
being initialized instead.

Only PHY2 on H616 has a clk2 clock. No other PHY on H616 has a clk2
clock, so phy->clk2 is NULL in this path and disabling it is a no-op.
This is why disabling the wrong clock did not cause an additional
functional failure.

The temporary phy2->clk2 enable therefore remains unmatched, leaking a
clock enable reference each time this path is executed.

Disable the same PHY2 clk2 that was enabled for the auxiliary PMU access.

Fixes: b45c6d80325b ("phy: sun4i-usb: Introduce port2 SIDDQ quirk")
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Xu Rao <[email protected]>
---
Changes in v2:
- Explain why disabling phy->clk2 did not cause additional harm: no
  other PHY on H616 has clk2, so phy->clk2 is NULL and the operation is
  a no-op.
- Clarify that the concrete issue is the unmatched PHY2 clk2 enable.
- Add the Fixes tag and Andre's Reviewed-by.

 drivers/phy/allwinner/phy-sun4i-usb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index e2fbf8ccf99e..839856c09e30 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -318,7 +318,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 			writel(val, phy2->pmu + REG_HCI_PHY_CTL);
 		}

-		clk_disable_unprepare(phy->clk2);
+		clk_disable_unprepare(phy2->clk2);
 	}

 	if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
--
2.50.1