Re: [PATCH] arm64: dts: allwinner: sun50i-a64-olinuxino: Add RX delay

Roman Riabenko <[email protected]>
Newsgroups dev.linux.lists.linux-sunxi,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-devicetree
Message-ID <[email protected]>
У ср, 2026-08-19 у 15:48 +0200, Andrew Lunn пише:
> On Sat, Aug 15, 2026 at 03:53:16AM +0300, Roman Riabenko wrote:
> > The Ethernet on Olimex A64-OlinuXino computers requires an RX delay
> > greater than 0. If the value is not set or is 0, packet loss in the
> > downlink direction is severe enough to interfere with downloads and
> > disrupt software installation.
> > 
> > The range of acceptable values is wide. The vendor has been
> > applying
> > 200 ps in its downstream DTs since 2021. This patch matches that
> > common practice.
> > 
> > Signed-off-by: Roman Riabenko <[email protected]>
> > ---
> >  arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
> > b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
> > index fd3794678c33..6c8b79c257b9 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
> > @@ -106,6 +106,7 @@ &emac {
> >  	phy-handle = <&ext_rgmii_phy>;
> >  	phy-supply = <&reg_dcdc1>;
> >  	allwinner,tx-delay-ps = <600>;
> > +	allwinner,rx-delay-ps = <200>;
> >  	status = "okay";
> >  };
> 
> The full node is:
> 
> &emac {
>         pinctrl-names = "default";
>         pinctrl-0 = <&rgmii_pins>;
>         phy-mode = "rgmii";
>         phy-handle = <&ext_rgmii_phy>;
>         phy-supply = <&reg_dcdc1>;
>         allwinner,tx-delay-ps = <600>;
>         status = "okay";
> };
> 
> Please take a read of:
> 
> https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/net/ethernet-controller.yaml#L287
> 
> phy-mode of "rgmii" is questionable. Does the PCB have extra long
> clock lines?

The PCB tracks for RX clock in comparison to RX data are approximately
the same in length in the PCB layout file (12 mm or so). The tracks for
TX clock in comparison to TX data are approximately the same as well
(roughly 14-16 mm). Thus, the tracks themselves do not appear to
implement the 2ns RGMII delay. Any delay from the tracks' lengths is
likely insignificant.

When I change the phy-mode to rgmii-id and remove allwinner,tx-delay-
ps, the connection is stable in both upstream and downstream direction.
There are no retries in my iperf3 tests. According to KSZ9031RNX
datasheet, it adds a typical 1.2 ns delay to RX_CLK with respect to
RX_DV and RXD by default, but no TX delay is provided by default. The
rgmii-id configuration causes the PHY driver to enable appropriate
internal RGMII delays.

I will submit a second version of the patch changing phy-mode to rgmii-
id and removing allwinner,tx-delay-ps.

Thank you for referring me to the linked document.

Roman
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