Re: [PATCH v2 RESEND] loongarch: retrieve CPU package ID from PPTT when available
Mingcong Bai <[email protected]>
| Newsgroups | dev.linux.lists.loongarch,org.kernel.vger.linux-kernel,org.kernel.vger.stable |
|---|---|
| Message-ID | <[email protected]> |
Hi Rong, 在 2026/7/5 17:36, Rong Bao 写道: > Currently, the LoongArch CPU topology initialization code calculates > each core's package ID by dividing its physical ID by > loongson_sysconf.cores_per_package. This relies on the assumption that > cores_per_package counts in the same domain as physical IDs. > > On Loongson 3B6000 (XB612B0V_1.2), cores_per_package matches the visible > core count -- 24 in this case. However, the physical IDs range from 0 to > 31 in a noncontinuous fashion: > > $ cat /proc/cpuinfo | grep -i -F 'global_id' > global_id : 0 > global_id : 1 > global_id : 4 > global_id : 5 > global_id : 6 > global_id : 7 > global_id : 8 > global_id : 9 > global_id : 10 > global_id : 11 > global_id : 14 > global_id : 15 > global_id : 16 > global_id : 17 > global_id : 20 > global_id : 21 > global_id : 22 > global_id : 23 > global_id : 26 > global_id : 27 > global_id : 28 > global_id : 29 > global_id : 30 > global_id : 31 > > Retrieve the exact package ID from ACPI PPTT when available, in the same > style as retrieving the core ID and thread ID in parse_acpi_topology(). > Use this information in loongson_init_secondary() when PPTT readout is > successful. The original division logic is kept as a fallback. > > Meanwhile, since some code paths like loongson3_cpufreq expect a > continuous integer sequence of package IDs in [0, MAX_PACKAGES) when > retrieving from cpu_data[], we also canonicalize the package ID to be > filled in parse_acpi_topology() to meet such an expectation. > > Cc: [email protected] > Co-developed-by: Xi Ruoyao <[email protected]> > Signed-off-by: Xi Ruoyao <[email protected]> > Signed-off-by: Rong Bao <[email protected]> Tested good on my Loongson XB612B0_V1.0 with an 8-core 3B6000: Architecture: loongarch64 CPU op-mode(s): 32-bit, 64-bit Address sizes: 48 bits physical, 48 bits virtual Byte Order: Little Endian CPU(s): 16 On-line CPU(s) list: 0-15 Model name: Loongson-3B6000 CPU family: Loongson-64bit Model: 0x10 Thread(s) per core: 2 Core(s) per socket: 8 Socket(s): 1 BogoMIPS: 4600.00 Flags: cpucfg lam lam_bh scq ual fpu lsx lasx crc32 complex crypto lspw lvz lbt_x86 lbt_arm lbt_mips Caches (sum of all): L1d: 512 KiB (8 instances) L1i: 512 KiB (8 instances) L2: 2 MiB (8 instances) L3: 32 MiB (1 instance) NUMA: NUMA node(s): 1 NUMA node0 CPU(s): 0-15 Vulnerabilities: Gather data sampling: Not affected Ghostwrite: Not affected Indirect target selection: Not affected Itlb multihit: Not affected L1tf: Not affected Mds: Not affected Meltdown: Not affected Mmio stale data: Not affected Old microcode: Not affected Reg file data sampling: Not affected Retbleed: Not affected Spec rstack overflow: Not affected Spec store bypass: Not affected Spectre v1: Mitigation; __user pointer sanitization Spectre v2: Not affected Srbds: Not affected Tsa: Not affected Tsx async abort: Not affected Vmscape: Not affected With that: Tested-by: Mingcong Bai <[email protected]> Best Regards, Mingcong Bai