[PATCH 02/11] bus: mhi: pci_generic: Add Data plane channels for QDU100 VF's

From: Vivek Pernamitta <[email protected]>

Add Data plane channels and event ring for QDU100 VF's. Disable
IRQ moderation for HW channels.

IP_HW1: Control configuration procedures over the L1 FAPI P5 interface
include initialization, termination, restart, reset, and error
notification. These procedures transition the PHY layer through IDLE,
CONFIGURED, and RUNNING states.

IP_HW2: Data plane configuration procedures control DL and UL frame
structures and transfer subframe data between L2/L3 software and PHY.
Supported procedures include subframe message transmission, SFN/SF
synchronization, and various transport channel operations.

Signed-off-by: Vivek Pernamitta <[email protected]>
Signed-off-by: Sivareddy Surasani <[email protected]>
---
 drivers/bus/mhi/host/pci_generic.c | 43 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
index b64b155e4bd7..bb3c5350a462 100644
--- a/drivers/bus/mhi/host/pci_generic.c
+++ b/drivers/bus/mhi/host/pci_generic.c
@@ -253,6 +253,20 @@ struct mhi_pci_dev_info {
 		.channel = ch_num,		\
 	}
 
+#define MHI_EVENT_CONFIG_HW_DATA_NO_IRQ_MOD(ev_ring, el_count, ch_num, cl_manage) \
+	{					\
+		.num_elements = el_count,	\
+		.irq_moderation_ms = 0,		\
+		.irq = (ev_ring) + 1,		\
+		.priority = 1,			\
+		.mode = MHI_DB_BRST_DISABLE,	\
+		.data_type = MHI_ER_DATA,	\
+		.hardware_event = true,		\
+		.client_managed = cl_manage,	\
+		.offload_channel = false,	\
+		.channel = ch_num,		\
+	}
+
 static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = {
 	MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2),
 	MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2),
@@ -278,6 +292,14 @@ static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = {
 
 };
 
+static const struct mhi_channel_config mhi_qcom_qdu100_vf_channels[] = {
+	/* HW channels */
+	MHI_CHANNEL_CONFIG_UL(104, "IP_HW1", 2048, 1),
+	MHI_CHANNEL_CONFIG_DL(105, "IP_HW1", 2048, 2),
+	MHI_CHANNEL_CONFIG_UL(106, "IP_HW2", 2048, 3),
+	MHI_CHANNEL_CONFIG_DL(107, "IP_HW2", 2048, 4),
+};
+
 static struct mhi_event_config mhi_qcom_qdu100_events[] = {
 	/* first ring is control+data ring */
 	MHI_EVENT_CONFIG_CTRL(0, 64),
@@ -294,6 +316,17 @@ static struct mhi_event_config mhi_qcom_qdu100_events[] = {
 	MHI_EVENT_CONFIG_SW_DATA(8, 512),
 };
 
+static struct mhi_event_config mhi_qcom_qdu100_vf_events[] = {
+	/* first ring is control+data ring */
+	MHI_EVENT_CONFIG_CTRL(0, 64),
+	/*  HW channels dedicated event ring */
+	MHI_EVENT_CONFIG_HW_DATA_NO_IRQ_MOD(1, 4096, 104, 0),
+	MHI_EVENT_CONFIG_HW_DATA_NO_IRQ_MOD(2, 4096, 105, 1),
+	MHI_EVENT_CONFIG_HW_DATA_NO_IRQ_MOD(3, 4096, 106, 0),
+	MHI_EVENT_CONFIG_HW_DATA_NO_IRQ_MOD(4, 4096, 107, 0),
+
+};
+
 static const struct mhi_controller_config mhi_qcom_qdu100_config = {
 	.max_channels = 128,
 	.timeout_ms = 120000,
@@ -303,11 +336,21 @@ static const struct mhi_controller_config mhi_qcom_qdu100_config = {
 	.event_cfg = mhi_qcom_qdu100_events,
 };
 
+static const struct mhi_controller_config mhi_qcom_qdu100_vf_config = {
+	.max_channels = 128,
+	.timeout_ms = 120000,
+	.num_channels = ARRAY_SIZE(mhi_qcom_qdu100_vf_channels),
+	.ch_cfg = mhi_qcom_qdu100_vf_channels,
+	.num_events = ARRAY_SIZE(mhi_qcom_qdu100_vf_events),
+	.event_cfg = mhi_qcom_qdu100_vf_events,
+};
+
 static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = {
 	.name = "qcom-qdu100",
 	.fw = "qcom/qdu100/xbl_s.melf",
 	.edl_trigger = true,
 	.config = &mhi_qcom_qdu100_config,
+	.vf_config = &mhi_qcom_qdu100_vf_config,
 	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
 	.dma_data_width = 32,
 	.vf_dma_data_width = 40,

-- 
2.34.1