[PATCH v2 3/3] arm64: dts: qcom: qcm6490-fairphone-fp5: add ST21NFCD NFC
Kristian Brox <[email protected]>
| Newsgroups | dev.linux.lists.oe-linux-nfc,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.netdev |
|---|---|
| Message-ID | <[email protected]> |
Enable the ST21NFCD on i2c9 (0x08), IRQ TLMM 41, reset TLMM 38 active-high. Compatible is st,st21nfcd (raw NCI). SYS_CLK is LN_BB_CLK2. VPS_IO is L18B (vreg_l18b). ese-present and uicc-present follow the public schematic (NFC_SWP1/SWP2: SWP_SE to SIM1, SWP_UICC to SIM2). Reader path is tested; SE/HCE is not. Signed-off-by: Kristian Brox <[email protected]> --- diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 29d6265..394237c 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -1004,7 +1004,23 @@ &i2c9 { status = "okay"; - /* ST21NFC NFC @ 28 */ + nfc@8 { + compatible = "st,st21nfcd"; + reg = <0x08>; + + interrupts-extended = <&tlmm 41 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_int_default>, <&nfc_reset_default>; + pinctrl-names = "default"; + + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + vdd-io-supply = <&vreg_l18b>; + + ese-present; + uicc-present; + }; + /* VL53L3 ToF @ 29 */ }; @@ -1649,6 +1665,21 @@ drive-strength = <2>; bias-pull-up; }; + + nfc_int_default: nfc-int-default-state { + pins = "gpio41"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + nfc_reset_default: nfc-reset-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; }; &uart5 {