[OPAE] [PATCH 3/3] pcie: Support port and fme enumeration within afu

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The device PCIe_DEVICE_ID_RCiEP0_SKX_P only supports fme and port
enumeration within afu. This behavior was supported by 0.9.0 but
not 0.13.0. This commit re-enables this feature.

Signed-off-by: Jia Zhang <zhang.jia(a)linux.alibaba.com>
---
 drivers/fpga/intel/pcie.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 42 insertions(+), 2 deletions(-)

diff --git a/drivers/fpga/intel/pcie.c b/drivers/fpga/intel/pcie.c
index c5483d6..7eb2146 100644
--- a/drivers/fpga/intel/pcie.c
+++ b/drivers/fpga/intel/pcie.c
@@ -516,6 +516,32 @@ static void build_info_free(struct build_feature_devs_=
info *binfo)
 }
 =

 /*
+ * FPGA hardware bug, FME/PORT GUID didn't follow the UUID/GUID rules, it
+ * it reported at:
+ *    https://hsdes.intel.com/appstore/article/#/1504370325
+ */
+#define FEATURE_FME_GUID "f9e17764-38f0-82fe-e346-524ae92aafbf"
+#define FEATURE_PORT_GUID "6b355b87-b06c-9642-eb42-8d139398b43a"
+
+static bool feature_is_afu_fme(struct feature_afu_header *afu_hdr)
+{
+	uuid_le u;
+
+	uuid_le_to_bin(FEATURE_FME_GUID, &u);
+
+	return !uuid_le_cmp(u, afu_hdr->guid);
+}
+
+static bool feature_is_afu_port(struct feature_afu_header *afu_hdr)
+{
+	uuid_le u;
+
+	uuid_le_to_bin(FEATURE_PORT_GUID, &u);
+
+	return !uuid_le_cmp(u, afu_hdr->guid);
+}
+
+/*
  * UAFU GUID is dynamic as it can be changed after FME downloads different
  * Green Bitstream to the port, so we treat the unknown GUIDs which are
  * attached on port's feature list as UAFU.
@@ -883,11 +909,25 @@ static int parse_feature_afus(struct build_feature_de=
vs_info *binfo,
 		afu_hdr =3D (struct feature_afu_header *) (hdr + 1);
 		header.csr =3D readq(&afu_hdr->csr);
 =

-		if (feature_is_UAFU(binfo)) {
+		if (feature_is_afu_fme(afu_hdr)) {
+			ret =3D parse_feature_fme(binfo, hdr);
+			check_features_header(binfo->pdev, hdr, FPGA_DEVT_FME, 0);
+			binfo->pfme_hdr =3D hdr;
+			if (ret)
+				return ret;
+		} else if (feature_is_afu_port(afu_hdr)) {
+			ret =3D parse_feature_port(binfo, hdr);
+			check_features_header(binfo->pdev, hdr, FPGA_DEVT_PORT, 0);
+			enable_port_uafu(binfo, hdr);
+			if (ret)
+				return ret;
+		} else if (feature_is_UAFU(binfo)) {
 			ret =3D parse_feature_port_uafu(binfo, hdr);
 			if (ret)
 				return ret;
-		}
+		} else
+			dev_info(&binfo->pdev->dev, "AFU GUID %pUl is not supported yet.\n",
+				 afu_hdr->guid.b);
 =

 		if (!header.next_afu)
 			break;
-- =

2.12.2


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