Re: [OPAE] Main Memory Access from FPGA

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C0 read and C1 write requests go to main memory buffers pinned with fpgaPre=
pareBuffer(). The transactions will use whatever physical channels are atta=
ched to the FPGA, which might be PCIe. The result is reads/writes from/to m=
ain memory.

-Michael

From: David Nicuesa <david.nicuesa.aranda(a)gmail.com>
Date: Thursday, February 7, 2019 at 11:23 AM
To: "Adler, Michael" <michael.adler(a)intel.com>, "opae(a)lists.01.org" <op=
ae(a)lists.01.org>
Subject: Re: [OPAE] Main Memory Access from FPGA

Hello Michael,

thanks for the quick response.

So, correct me if I'm wrong, MMIO goes into the c2 on RTL, and Reads/Writes=
 are managed through c0 and c1, right?
This way I can allocate a buffer through software using  fpgaPrepareBuffer =
and access that buffer from software as a regular array, and using c0/c1 th=
e AFU is able to work with it and those will be actual main memory accesses=
, not PCIe transactions.

Thank you very much for the help.

Regards,
David

El jue., 7 feb. 2019 a las 16:41, Adler, Michael (<michael.adler(a)intel.co=
m<mailto:michael.adler(a)intel.com>>) escribi=C3=B3:
The CCI-P interface differentiates between MMIO (memory mapped I/O) and mai=
n memory read/write requests. MMIO is an FPGA-side address space, mainly us=
ed for implementing FPGA-side CSRs. Those CSRs are exposed in the software=
=E2=80=99s address space but actually result in PCIe transactions to the FP=
GA.

CCI-P=E2=80=99s main memory read/write requests are exactly what you are as=
king for: DMA to host main memory. The primary address space used for those=
 requests is a =E2=80=9Cphysical=E2=80=9D I/O address space that maps to ho=
st physical addresses. It is also possible to use virtual addresses on the =
FPGA that correspond to the software=E2=80=99s virtual address space. For t=
hat you can use the MPF VTP extension. See section 3 of the tutorial<https:=
//github.com/OPAE/intel-fpga-bbb/tree/master/samples/tutorial/03_ccip>.

-Michael

From: OPAE <opae-bounces(a)lists.01.org<mailto:opae-bounces(a)lists.01.org>=
> on behalf of David Nicuesa <david.nicuesa.aranda(a)gmail.com<mailto:david=
.nicuesa.aranda(a)gmail.com>>
Date: Thursday, February 7, 2019 at 9:53 AM
To: "opae(a)lists.01.org<mailto:opae(a)lists.01.org>" <opae(a)lists.01.org<=
mailto:opae(a)lists.01.org>>
Subject: [OPAE] Main Memory Access from FPGA

Hi all,

I'm getting started with the examples, specifically with the hello_world fr=
om the intel-fpga-bbb<https://github.com/OPAE/intel-fpga-bbb/tree/master/sa=
mples/tutorial/01_hello_world> repository. Everything works just fine but I=
 was wondering if it is possible for me to access the Main Memory (Not IO) =
from the FPGA using the CCI protocol.

I have an rtl to sum two vectors, so my idea was to provide the addresses f=
or those two vectors from the software application, allocated in General Pu=
rpose Memory. This way, ideally, the FPGA should be able to access those ve=
ctors without having a shared buffer (MMIO).

Is it possible to do this, maybe using some MPF extension? In case this is =
not feasible, I should allocate a shared buffer in MMIO space and then comu=
nicate the vectors through that buffer, right?

Thanks!

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--===============6613478253623594195==--