Re: Regression in split ARM MMIO timer driver

On Sat, May 09, 2026 at 06:58:00PM +0100, Marc Zyngier wrote:
> On Sat, 09 May 2026 13:19:56 +0100,
> Sudeep Holla <[email protected]> wrote:
> > 
> > On Fri, May 08, 2026 at 03:48:14PM -0400, Jack Matthews wrote:
> > > Hello,
> > >
> > > I am working on mainlining an old chip, Qualcomm's MDM9625 modem.
> > > I had previously booted 6.17-rc3 before putting this project to the side,
> > > but when I restarted work on 7.0 I was unable to boot. 
> > > I have bisected this to commit 0f67b56d84b4c49adfd61f19f81f84ec613ab51a
> > > (https://lore.kernel.org/all/[email protected]/) and
> > > reverting this commit makes the device boot successfully. Unfortunately I do
> > > not have access to low level debugging such as UART so I have not been able
> > > to pinpoint exactly what is missing.
> > > My changes for this chip are all available here in case it is an issue of my
> > > own doing: https://github.com/jackmthws/linux/commits/mdm9625-latest/.
> > 
> > Looking briefly into the DTS file, I couldn't find the sysreg based
> > arch timer node in the DT. It could be just an overlook unless there
> > is some issue with it that it's not added. After the above mentioned
> > commit, the MMIO timer gets initialised bit late in the boot and
> > could be the reason for boot failure. Unless you have intentionally
> > not added it, I would suggest to add it and try.
> 
> Ah, that's a good point. Not having per-CPU timers is not going to
> fly, I'm afraid. The MMIO timer will kick in very late, and we
> probably need to schedule threads way before that.
> 
> This looks to be a single Cortex-A5 however, not an A5MP, meaning it
> does not have the TWD, and relies on a global timer, which is a
> terrible thing to have. Not to mention that MMIO accesses on the
> counter is going to be even worse.
> 

Ah, my bad I misread it as Cortex-A15 and not Cortex-A5, so assumed
missing sysreg based per-cpu arch timers.

-- 
Regards,
Sudeep