Re: [PATCH v8 3/4] arm64: dts: nuvoton: npcm845: Add peripheral nodes

On Wed, 8 Jul 2026 at 20:15, <[email protected]> wrote:
>
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [High] Missing required DT aliases for the FIU nodes, which will cause the FIU SPI driver to fail to probe.
> - [Medium] The `fiu0`, `fiu1`, and `fiu3` SPI controller nodes are missing the required `memory` register region.
> --
>
> --- Patch [3]: [PATCH v8 3/4] arm64: dts: nuvoton: npcm845: Add peripheral nodes ---
> commit 206c681ed8ed3430aac99224e79975aed3d5da1b
> Author: Tomer Maimon <[email protected]>
>
> arm64: dts: nuvoton: npcm845: Add peripheral nodes
>
> Extend the NPCM845 SoC DTSI with the peripheral controller nodes needed
> by the evaluation board and downstream platforms.
>
> > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
>
> [ ... ]
>
> > +             fiu0: spi@fb000000 {
>
> [Severity: High]
> Will the FIU SPI driver fail to probe due to missing device tree aliases?
>
> During driver initialization, spi-npcm-fiu.c calls
> of_alias_get_id(dev->of_node, "fiu") to determine the controller index.
> Since the fiu0, fiu1, fiu3, and fiux nodes do not have corresponding aliases
> defined, this lookup will return a negative error code.
>
> This causes the driver to return -EINVAL and fail to probe. The
> nuvoton,npcm-fiu binding also mandates that all FIU controllers be
> represented in the aliases node.
>
> > +                     compatible = "nuvoton,npcm845-fiu";
> > +                     #address-cells = <1>;
> > +                     #size-cells = <0>;
> > +                     reg = <0x0 0xfb000000 0x0 0x1000>;
> > +                     reg-names = "control";
>
Yes, and it is defined in the DTS file and explained in dt-binding.
> [Severity: Medium]
> Will this cause a fallback to slower indirect PIO reads?
Without setting the memory reg, the driver will use UMA commands to do
the read operation instead of direct reads.
>
> The fiu0, fiu1, and fiu3 SPI controller nodes omit the second 'memory'
> register region and its corresponding 'memory' reg-name.
>
> When the SPI controller probes, it looks up the memory region using:
> platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory")
>
> If it fails to find the memory resource, the driver sets desc->nodirmap = true
> which disables direct memory-mapped reads. The dt binding for nuvoton,npcm-fiu
> requires both 'control' and 'memory' regions to be specified.
>
> > +                     clocks =  <&clk NPCM8XX_CLK_SPI0>;
> > +                     status = "disabled";
> > +             };
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3

Thansk,

Tomer