Re: [PATCH 1/2] mips: econet: add multi-vpe capability to EN751221

On 28/07/2026 21:06, [email protected] wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] Unconditionally masking hardware interrupts in en751221_init_secondary breaks the secondary CPU's timer if the system boots with VEIC disabled.

I didn't mention it in the commit message because SMP_MT implies _EI and 
_VI, enabling VEIC. But lines 6 and 7 are in fact unconditionally dead 
on the EN751221, the classical MIPS timer is not present.

Thanks,

Caleb

> --
>
> --- Patch [1]: [PATCH 1/2] mips: econet: add multi-vpe capability to EN751221 ---
> commit 29d4bfd90711d72516d1c7a3132dda2ae50742fc
> Author: Caleb James DeLisle <[email protected]>
>
> mips: econet: add multi-vpe capability to EN751221
>
> This commit registers SMP_MT on startup and overrides init_secondary with
> CPU interrupt unmasking required by the EN751221 VEIC intc hardware.
>
>> diff --git a/arch/mips/econet/init.c b/arch/mips/econet/init.c
>> --- a/arch/mips/econet/init.c
>> +++ b/arch/mips/econet/init.c
> [ ... ]
>> +static void en751221_init_secondary(void)
>> +{
>> +	write_c0_status((read_c0_status() & ~ST0_IM) |
>> +		(STATUSF_IP0 | STATUSF_IP1));
>> +}
>> +
>> +static int __init en751221_register_vsmp_smp_ops(void)
>> +{
>> +	if (!cpu_has_mipsmt)
>> +		return -ENODEV;
> [Severity: High]
> If the system boots with VEIC disabled (e.g., falling back to cascading mode),
> will this break the secondary CPU's timer?
>
> By registering these VEIC-specific SMP operations here without checking
> cpu_has_veic, en751221_init_secondary() will execute on the secondary CPU.
>
> Since en751221_init_secondary() clears ST0_IM unconditionally, it masks
> hardware interrupts including the timer interrupt. Could this lead to
> boot stalls or RCU hangs on non-VEIC setups?
>
>> +
>> +	en75_smp_ops = vsmp_smp_ops;
>> +	en75_smp_ops.init_secondary = en751221_init_secondary;
>> +	register_smp_ops(&en75_smp_ops);
>> +	return 0;
>> +}