Re: [PATCH v4 06/48] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields

On Fri, 2026-07-24 at 11:14 +0000, [email protected] wrote:
> [Severity: High]
> This is a pre-existing issue, but since this patch updates the
> ICC_CR0_EL1
> sysreg definitions, is it possible that context synchronization
> events are
> missing after writes to these control registers?
> 
> For example, in drivers/irqchip/irq-gic-
> v5.c:gicv5_cpu_disable_interrupts(),
> SYS_ICC_CR0_EL1 is written without an immediate isb():
> 
> drivers/irqchip/irq-gic-v5.c:gicv5_cpu_disable_interrupts() {
> 	cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 0);
> 	write_sysreg_s(cr0, SYS_ICC_CR0_EL1);
> }
> 
> A similar pattern occurs in gicv5_cpu_enable_interrupts(),
> write_ppi_sysreg_s(),
> and gicv5_ppi_priority_init() for registers like SYS_ICC_PCR_EL1, 
> SYS_ICC_PPI_SPENDR0_EL1, and SYS_ICC_PPI_PRIORITYR0_EL1. Is there a
> risk of
> operating under a stale pipeline configuration if an ISB does not
> immediately
> follow these writes?

Ah, this again? No. This is not an issue, and "stale pipeline
configuration" really isn't what we'd get here (or a thing).

Thanks,
Sascha