Re: [PATCH v5 09/17] dt-bindings: riscv: Add Zic64b extension description

On Wed, 01 Jul 2026 13:42:50 +0000, [email protected] wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] Incomplete schema validation for Zic64b cache block sizes. The schema correctly constrains the CMO-specific block sizes (riscv,cbom-block-size, etc.) to 64 bytes when the zic64b extension is present, but fails to constrain the standard CPU cache block size properties (d-cache-block-size, d-cache-line-size, i-cache-block-size, i-cache-line-size).
> --
>
> commit 31237d196ec63ec596da17f48f8410b2eee95c15
> Author: Guodong Xu <[email protected]>
>
> dt-bindings: riscv: Add Zic64b extension description
>
> Zic64b mandates that cache blocks are 64 bytes in size and naturally
> aligned in the address space. It is a mandatory extension of both the
> RVA22 (U64/S64) and RVA23 (U64/S64) profiles, ratified with RISC-V
> Profiles Version 1.0.
>
> Document it so it can be described in the riscv,isa-extensions property,
> alongside the related Zicbom/Zicbop/Zicboz cache-block extensions. Since
> Zic64b fixes the cache block size at 64 bytes, also add a schema check
> requiring any present cbom/cbop/cboz block size to be 64.
>
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index f4dd34d446c02..bbd442cfbd904 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
>
> [ ... ]
>
> > @@ -1142,6 +1148,20 @@ allOf:
> >            not:
> >              contains:
> >                const: zilsd
> > +  # Zic64b mandates 64-byte naturally aligned cache blocks
> > +  - if:
> > +      properties:
> > +        riscv,isa-extensions:
> > +          contains:
> > +            const: zic64b
> > +    then:
> > +      properties:
> > +        riscv,cbom-block-size:
> > +          const: 64
> > +        riscv,cbop-block-size:
> > +          const: 64
> > +        riscv,cboz-block-size:
> > +          const: 64
>
> [Severity: Medium]
> Should the standard CPU cache properties like d-cache-block-size,
> d-cache-line-size, i-cache-block-size, and i-cache-line-size also be
> constrained to 64 here?

No. Not constrained on purpose. Zic64b's mandate is the cache block size
the CMO instructions (cbom/cbop/cboz) operate on, which is exactly what
the riscv,cbom/cbop/cboz-block-size properties describe.

The d/i-cache-block-size and d/i-cache-line-size properties describe the
implementation's cache geometry, which Zic64b does not fix: the
profile v1.0 [1] spec's note under Zic64b explicitly permits
implementations to use longer physical cache blocks (with 64-byte
sub-blocks) or shorter ones (sequencing operations across the blocks
comprising a 64-byte block). Constraining the cache geometry properties
to 64 here would reject those conforming designs.

[1]: 6.1.2. RVA22U64 Mandatory Extensions, RISC-V Profiles Version 1.0,
     April 2, 2023

Guodong