Re: [PATCH v1 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap

On Thu, Aug 20, 2026 at 08:42:07AM +0000, [email protected] wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] The commit message inaccurately claims to change the 'CPU address', but the patch actually changes the 'PCI address'.
> --
>
> --- Patch [1]: [PATCH v1 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap ---
> commit 1e55a58df93bb33b1e5b78cb2403b958366907f0
> Author: Richard Zhu <[email protected]>
>
> arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap
>
> This commit updates the device tree configuration for the PCIe controllers
> on the imx95 platform. It adjusts the ranges property to prevent memory
> window overlaps.
>
> > Move the PCIe non-prefetchable memory CPU address from 0xe0000000
> > to 0x10000000 to avoid overlap with DRAM.
>
> [Severity: Medium]
> Is this description of the change accurate?
>
> The device tree ranges property uses the format:
> <PCI_HI PCI_MID PCI_LO CPU_HI CPU_LO SIZE_HI SIZE_LO>
>
> > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> > @@ -1948,7 +1948,7 @@ pcie0: pcie@4c300000 {
> [ ... ]
> >  			reg-names = "dbi", "config", "atu", "app";
> >  			ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
> > -				 <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
> > +				 <0x82000000 0x0 0x10000000 0x9 0xe0000000 0x0 0x10000000>,
>
> Looking at the modification to pcie0, the CPU (parent) bus address is
> represented by the 4th and 5th cells (0x9 0xe0000000). These cells remain
> unchanged in this patch.
>
> The cell that is updated from 0xe0000000 to 0x10000000 is the 3rd cell,
> which corresponds to the lower 32 bits of the PCI (child) bus address.
>
> Could the commit message be clarified to state that the PCI address is
> being changed, or was the intent to actually update the CPU address in
> the 5th cell?

Sashiko is correct, update your commit message, it is not "cpu address"

it is "PCI bus address", you'd better refer to old sashio thread or
prevous discuss link.

Frank

>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1