Re: [PATCH 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC
Manivannan Sadhasivam <[email protected]> Tue, 19 May 2026 19:11:19 +0530
| Newsgroups | dev.linux.lists.sashiko,org.kernel.vger.linux-pci |
|---|---|
| Message-ID | <7gl7nidvytiu64qwssp55jpcetagefsnwb7ylq54miegmekdyh@rjhietvwqntu> |
On Fri, May 08, 2026 at 01:21:34AM +0000, [email protected] wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Low] The compatible string and filename violate the established Qualcomm PCIe naming pattern. > -- > > commit 332996956780b2d8736ee1fcd6b38c1627f71689 > Author: Matthew Leung <[email protected]> > > dt-bindings: PCI: qcom: Document the Hawi PCIe Controller > > Add a dedicated schema for the PCIe controllers found on the Hawi > platform. > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml > > new file mode 100644 > > index 0000000000000..154bc88e59694 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml > > This isn't a bug, but is there a reason this file isn't named > qcom,pcie-hawi.yaml? The rest of the Qualcomm PCIe Root Complex bindings > strictly follow the qcom,pcie-<soc> naming pattern, such as > qcom,pcie-sc7280.yaml and qcom,pcie-sm8550.yaml. > > [ ... ] > > > +properties: > > + compatible: > > + const: qcom,hawi-pcie > > Should this compatible string also be changed to qcom,pcie-hawi to maintain > consistency with the other Qualcomm Root Complex definitions across the > subsystem? > All other IP blocks follow the 'vendor,soc-ip' naming convention and only PCIe differs from that. And we already have some SoCs using 'vendor,soc-ip' convention for PCIe: git grep -r "qcom.*-pcie\"" arch/arm64/boot/dts/qcom/ arch/arm64/boot/dts/qcom/glymur.dtsi: compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; arch/arm64/boot/dts/qcom/glymur.dtsi: compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; arch/arm64/boot/dts/qcom/glymur.dtsi: compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; arch/arm64/boot/dts/qcom/glymur.dtsi: compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; arch/arm64/boot/dts/qcom/kaanapali.dtsi: compatible = "qcom,kaanapali-pcie", "qcom,pcie-sm8550"; arch/arm64/boot/dts/qcom/sar2130p.dtsi: compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550"; arch/arm64/boot/dts/qcom/sar2130p.dtsi: compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550"; I talked to Krzk offline and concluded that to align with the common convention, we should keep it as 'qcom,hawi-pcie' and use 'vendor,soc-ip' from here on for PCIe. - Mani -- மணிவண்ணன் சதாசிவம்