Re: [PATCH] arm64: dts: bst: enable eMMC controller in C1200

Hello:

This patch was applied to soc/soc.git (for-next)
by Gordon Ge <[email protected]>:

On Fri, 12 Jun 2026 08:40:23 +0800 you wrote:
> Add mmc0 node for the DWCMSHC SDHCI controller with basic configuration
> (disabled by default) and fixed clock definition in bstc1200.dtsi.
> 
> Enable mmc0 with board-specific configuration including 8-bit bus
> width and reserved SRAM bounce buffer on the CDCU1.0 ADAS 4C2G board.
> 
> The bounce buffer in reserved SRAM addresses hardware constraints
> where the eMMC controller cannot access main system memory through
> SMMU due to a hardware bug, and all DRAM is located outside the
> 4GB boundary.
> 
> [...]

Here is the summary with links:
  - arm64: dts: bst: enable eMMC controller in C1200
    https://git.kernel.org/soc/soc/c/6191a61ec9d9

You are awesome, thank you!
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