[PATCH 09/10] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT

Enable the Ambarella ARMv8 platform Kconfig, add the CV75 SoC and
EVK device trees, and select the Ambarella UART in the arm64
defconfig for console bring-up.

Signed-off-by: Long Zhao <[email protected]>
---
 arch/arm64/Kconfig.platforms               |   9 ++
 arch/arm64/boot/dts/Makefile               |   1 +
 arch/arm64/boot/dts/ambarella/Makefile     |   3 +
 arch/arm64/boot/dts/ambarella/cv75-evk.dts |  30 ++++
 arch/arm64/boot/dts/ambarella/cv75.dtsi    | 151 +++++++++++++++++++++
 arch/arm64/configs/defconfig               |   3 +
 6 files changed, 197 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ambarella/Makefile
 create mode 100644 arch/arm64/boot/dts/ambarella/cv75-evk.dts
 create mode 100644 arch/arm64/boot/dts/ambarella/cv75.dtsi

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index d2acfac73003..166430ddb3c9 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -26,6 +26,15 @@ config ARCH_SUNXI
        help
          This enables support for Allwinner sunxi based SoCs like the A64.

+config ARCH_AMBARELLA
+       bool "Ambarella SoC family"
+       select ARM_PSCI
+       select HAVE_ARM_ARCH_TIMER
+       select PINCTRL
+       select PINCTRL_AMB
+       help
+         This enables support for the ARM64 based Ambarella SoCs like CV75=
.
+
 config ARCH_ALPINE
        bool "Annapurna Labs Alpine platform"
        select ALPINE_MSI if PCI
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index fc726b215f12..f1709eb5d915 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y +=3D airoha
 subdir-y +=3D allwinner
 subdir-y +=3D altera
 subdir-y +=3D amazon
+subdir-y +=3D ambarella
 subdir-y +=3D amd
 subdir-y +=3D amlogic
 subdir-y +=3D apm
diff --git a/arch/arm64/boot/dts/ambarella/Makefile b/arch/arm64/boot/dts/a=
mbarella/Makefile
new file mode 100644
index 000000000000..ddca3d7b18cc
--- /dev/null
+++ b/arch/arm64/boot/dts/ambarella/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+dtb-$(CONFIG_ARCH_AMBARELLA) +=3D cv75-evk.dtb
diff --git a/arch/arm64/boot/dts/ambarella/cv75-evk.dts b/arch/arm64/boot/d=
ts/ambarella/cv75-evk.dts
new file mode 100644
index 000000000000..42a0fe24b83b
--- /dev/null
+++ b/arch/arm64/boot/dts/ambarella/cv75-evk.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Ambarella CV75 EVK board
+ */
+
+/dts-v1/;
+
+#include "cv75.dtsi"
+
+/ {
+       model =3D "Ambarella CV75 EVK Board";
+       compatible =3D "ambarella,cv75-evk", "ambarella,cv75";
+
+       aliases {
+               serial0 =3D &uart0;
+       };
+
+       chosen {
+               stdout-path =3D &uart0;
+       };
+
+       memory@200000 {
+               device_type =3D "memory";
+               reg =3D <0x0 0x00200000 0x0 0x07e00000>;
+       };
+};
+
+&uart0 {
+       status =3D "okay";
+};
diff --git a/arch/arm64/boot/dts/ambarella/cv75.dtsi b/arch/arm64/boot/dts/=
ambarella/cv75.dtsi
new file mode 100644
index 000000000000..7c6a61f473ef
--- /dev/null
+++ b/arch/arm64/boot/dts/ambarella/cv75.dtsi
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Ambarella CV75 SoC
+ *
+ * Boot peripheral: UART0 console.
+ * Clocks: a single ambarella,cv75-rct provider.
+ */
+
+#include <dt-bindings/clock/ambarella,cv75-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/ambarella,pinctrl.h>
+
+/ {
+       compatible =3D "ambarella,cv75";
+       interrupt-parent =3D <&gic>;
+       #address-cells =3D <2>;
+       #size-cells =3D <2>;
+
+       osc: oscillator {
+               compatible =3D "fixed-clock";
+               #clock-cells =3D <0>;
+               clock-output-names =3D "osc";
+               clock-frequency =3D <24000000>;
+       };
+
+       psci {
+               compatible =3D "arm,psci-0.2";
+               method =3D "smc";
+       };
+
+       cpus {
+               #address-cells =3D <1>;
+               #size-cells =3D <0>;
+
+               cpu@0 {
+                       compatible =3D "arm,cortex-a76";
+                       device_type =3D "cpu";
+                       reg =3D <0x000>;
+                       enable-method =3D "psci";
+               };
+
+               cpu@1 {
+                       compatible =3D "arm,cortex-a76";
+                       device_type =3D "cpu";
+                       reg =3D <0x100>;
+                       enable-method =3D "psci";
+               };
+       };
+
+       gic: interrupt-controller@fff0100000 {
+               compatible =3D "arm,gic-400";
+               #interrupt-cells =3D <3>;
+               #address-cells =3D <0>;
+               #size-cells =3D <1>;
+               interrupt-controller;
+               reg =3D <0xff 0xf0101000 0x0 0x1000>,
+                     <0xff 0xf0102000 0x0 0x2000>,
+                     <0xff 0xf0104000 0x0 0x2000>,
+                     <0xff 0xf0106000 0x0 0x2000>;
+               interrupts =3D <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYP=
E_LEVEL_HIGH)>;
+       };
+
+       timer {
+               compatible =3D "arm,armv8-timer";
+               interrupts =3D <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TY=
PE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE=
_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE=
_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE=
_LEVEL_LOW)>;
+       };
+
+       soc {
+               compatible =3D "simple-bus";
+               #address-cells =3D <2>;
+               #size-cells =3D <2>;
+               ranges;
+
+               /* Clock provider and shared system registers. */
+               rct: clock-controller@ffed080000 {
+                       compatible =3D "ambarella,cv75-rct", "syscon";
+                       reg =3D <0xff 0xed080000 0x0 0x1000>;
+                       clocks =3D <&osc>;
+                       clock-names =3D "osc";
+                       #clock-cells =3D <1>;
+
+                       assigned-clocks =3D <&rct CV75_GCLK_UART0>;
+                       assigned-clock-parents =3D <&osc>;
+                       assigned-clock-rates =3D <24000000>;
+               };
+
+               apb@ffe4000000 {
+                       compatible =3D "simple-bus";
+                       #address-cells =3D <1>;
+                       #size-cells =3D <1>;
+                       reg =3D <0xff 0xe4000000 0x0 0x01000000>;
+                       ranges =3D <0xe4000000 0xff 0xe4000000 0x01000000>;
+
+                       uart0: serial@e4000000 {
+                               compatible =3D "ambarella,cv75-uart", "amba=
rella,uart";
+                               reg =3D <0xe4000000 0x1000>;
+                               interrupts =3D <GIC_SPI 170 IRQ_TYPE_LEVEL_=
HIGH>;
+                               clocks =3D <&rct CV75_GCLK_UART0>;
+                               pinctrl-names =3D "default";
+                               pinctrl-0 =3D <&uart0_pins>;
+                               status =3D "disabled";
+                       };
+
+                       pinctrl: pinctrl@e4013000 {
+                               compatible =3D "ambarella,cv75-pinctrl";
+                               #address-cells =3D <1>;
+                               #size-cells =3D <0>;
+                               reg =3D <0xe4013000 0x1000>, <0xe4014000 0x=
1000>,
+                                     <0xe4015000 0x1000>, <0xe4010000 0x10=
00>;
+                               reg-names =3D "gpio0", "gpio1", "gpio2", "i=
omux";
+                               interrupts =3D <GIC_SPI 163 IRQ_TYPE_LEVEL_=
HIGH>,
+                                            <GIC_SPI 164 IRQ_TYPE_LEVEL_HI=
GH>,
+                                            <GIC_SPI 165 IRQ_TYPE_LEVEL_HI=
GH>;
+                               ambarella,drive-strength-syscon =3D <&rct>;
+                               ambarella,pull-syscon =3D <&s_scratchpad_sy=
scon>;
+
+                               gpio: gpio@0 {
+                                       reg =3D <0>;
+                                       gpio-controller;
+                                       #gpio-cells =3D <2>;
+                                       gpio-ranges =3D <&pinctrl 0 0 95>;
+                                       interrupt-controller;
+                                       #interrupt-cells =3D <2>;
+                               };
+
+                               uart0_pins: uart0-pins {
+                                       function =3D "uart0";
+                                       pinmux =3D <AMBA_PINMUX(44, 1)>,
+                                                <AMBA_PINMUX(45, 1)>;
+                               };
+                       };
+               };
+
+               ahb@ffe0000000 {
+                       compatible =3D "simple-bus";
+                       #address-cells =3D <1>;
+                       #size-cells =3D <1>;
+                       reg =3D <0xff 0xe0000000 0x0 0x01000000>;
+                       ranges =3D <0xe0000000 0xff 0xe0000000 0x01000000>;
+
+                       s_scratchpad_syscon: scratchpad@e002e000 {
+                               compatible =3D "ambarella,cv75-sec-scratchp=
ad",
+                                            "ambarella,sec-scratchpad", "s=
yscon";
+                               reg =3D <0xe002e000 0x1000>;
+                       };
+               };
+       };
+};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ad3bd3d9507b..64e8fbe43d27 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -36,6 +36,7 @@ CONFIG_CRASH_DUMP=3Dy
 CONFIG_ARCH_ACTIONS=3Dy
 CONFIG_ARCH_AIROHA=3Dy
 CONFIG_ARCH_SUNXI=3Dy
+CONFIG_ARCH_AMBARELLA=3Dy
 CONFIG_ARCH_ALPINE=3Dy
 CONFIG_ARCH_APPLE=3Dy
 CONFIG_ARCH_ARTPEC=3Dy
@@ -567,6 +568,8 @@ CONFIG_SERIAL_8250_OMAP=3Dy
 CONFIG_SERIAL_8250_MT6577=3Dy
 CONFIG_SERIAL_8250_UNIPHIER=3Dy
 CONFIG_SERIAL_OF_PLATFORM=3Dy
+CONFIG_SERIAL_AMBARELLA=3Dy
+CONFIG_SERIAL_AMBARELLA_CONSOLE=3Dy
 CONFIG_SERIAL_AMBA_PL011=3Dy
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=3Dy
 CONFIG_SERIAL_MESON=3Dy
--
2.34.1

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