Re: [PATCH v2 3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver
Chen Wang <[email protected]>
| Newsgroups | dev.linux.lists.sophgo,org.infradead.lists.linux-riscv,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci |
|---|---|
| Message-ID | <MAUPR01MB1107224119A8D402FEBE5E2D0FE09A@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM> |
On 9/10/2025 10:34 PM, Bjorn Helgaas wrote: > On Wed, Sep 10, 2025 at 10:08:39AM +0800, Chen Wang wrote: >> From: Chen Wang <[email protected]> >> >> Add support for PCIe controller in SG2042 SoC. The controller >> uses the Cadence PCIe core programmed by pcie-cadence*.c. The >> PCIe controller will work in host mode only, supporting data >> rate(gen4) and lanes(x16 or x8). > Strictly speaking, "gen4" is a spec revision, not a data rate. > Include the GT/s rate instead or in addition. We can fix this when > merging if there's no other reason to repost (I assume you mean 16 > GT/s). Will also add spaces before the open "(". Yes, I meant 16 GT/s. Please help fix this when merging together with dropping period at end of subject for the [2/7], if no repost. Thanks, Chen