Re: [PATCH v3 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042
Chen Wang <[email protected]>
| Newsgroups | dev.linux.lists.sophgo,org.infradead.lists.linux-riscv,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci |
|---|---|
| Message-ID | <MAUPR01MB110728EEF983FFA560BFEB0B1FE18A@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM> |
On 9/20/2025 3:42 PM, Manivannan Sadhasivam wrote: > On Fri, Sep 12, 2025 at 10:36:50AM +0800, Chen Wang wrote: >> From: Chen Wang <[email protected]> >> >> Add PCIe controller nodes in DTS for Sophgo SG2042. >> Default they are disabled. >> >> Signed-off-by: Inochi Amaoto <[email protected]> >> Signed-off-by: Han Gao <[email protected]> >> Signed-off-by: Chen Wang <[email protected]> >> --- >> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++ >> 1 file changed, 88 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi >> index b3e4d3c18fdc..b521f674283e 100644 >> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi >> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi >> @@ -220,6 +220,94 @@ clkgen: clock-controller@7030012000 { >> #clock-cells = <1>; >> }; >> >> + pcie_rc0: pcie@7060000000 { >> + compatible = "sophgo,sg2042-pcie-host"; >> + device_type = "pci"; >> + reg = <0x70 0x60000000 0x0 0x00800000>, >> + <0x40 0x00000000 0x0 0x00001000>; >> + reg-names = "reg", "cfg"; >> + linux,pci-domain = <0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, > PCI address of the I/O port starts from 0. So this should be: > > <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, > > Same comment for other nodes. > > With this fixed, > > Acked-by: Manivannan Sadhasivam <[email protected]> > > - Mani Thanks, I will fix this in next version. [......]