Re: [PATCH] PCI/sophgo: Avoid L0s and L1 on Sophgo 2044 PCIe Root Ports
Manivannan Sadhasivam <[email protected]>
| Newsgroups | dev.linux.lists.sophgo,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci |
|---|---|
| Message-ID | <[email protected]> |
On Fri, 09 Jan 2026 12:07:53 +0800, Inochi Amaoto wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2044 root port breaks as it advertises L0s and L1
> capabilities without supporting it.
>
> Mask the L0s and L1 Support advertised in Link Capabilities
> in the LINKCAP register SG2044 Root Ports, so the framework
> won't try to enable those states.
>
> [...]
Applied, thanks!
[1/1] PCI/sophgo: Avoid L0s and L1 on Sophgo 2044 PCIe Root Ports
commit: 613f3255a35a95f52575dd8c60b7ac9d711639ce
Best regards,
--
Manivannan Sadhasivam <[email protected]>