Re: [PATCH v4 0/5] Add initial Milk-V Duo S board support
Michael Opdenacker <[email protected]> Thu, 2 Apr 2026 13:47:32 +0000 (UTC)
| Newsgroups | dev.linux.lists.sophgo,org.infradead.lists.linux-riscv,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
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| Message-ID | <[email protected]> |
Hi Joshua On 4/2/26 2:29 PM, Joshua Milas wrote: > Hi Michael, > > Thanks for testing this. I am not seeing that issue on my arm64 or riscv side. > I am able to add an IP and do anything I can think of on the arm64 side. > > [ 96.618687] stmmaceth 4070000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 > [ 96.633977] stmmaceth 4070000.ethernet eth0: PHY [mdio_mux-0.0:01] driver [Generic PHY] (irq=POLL) > [ 96.676436] dwmac1000: Master AXI performs any burst length > [ 96.702852] stmmaceth 4070000.ethernet eth0: No Safety Features support found > [ 96.748740] stmmaceth 4070000.ethernet eth0: IEEE 1588-2002 Timestamp supported > [ 96.772880] stmmaceth 4070000.ethernet eth0: configuring for phy/internal link mode > [ 1359.377528] stmmaceth 4070000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off > > I can do the same on the riscv side but get a unhandled signal for TLS traffic > which I believe is unrelated as it doesn't happen on adding an IP. > > I'll send over my configs to see if that helps. I confirmed I managed to test the eth0 network interface on the riscv side using the configuration you shared. It would take me more time to test on arm64 :D| You can send a update with your checkpatch fixes. Tested-by: Michael Opdenacker <[email protected]> Thanks for everything! Cheers Michael. -- Root Commit Embedded Linux Training and Consulting https://rootcommit.com