[GIT PULL] RISC-V Sophgo Devicetrees for v7.2
Chen Wang <[email protected]> Wed, 3 Jun 2026 14:17:42 +0800
| Newsgroups | dev.linux.lists.sophgo,dev.linux.lists.soc,org.infradead.lists.linux-riscv |
|---|---|
| Message-ID | <MA5PR01MB1250024541E71412DDA04B4AAFE132@MA5PR01MB12500.INDPRD01.PROD.OUTLOOK.COM> |
Hey Arnd, Please pull this dt changes for RISC-V/Sophgo. BTW: Next PR, I will start using my new work email address: [email protected]. Thanks, Chen The following changes since commit 254f49634ee16a731174d2ae34bc50bd5f45e731: Linux 7.1-rc1 (2026-04-26 14:19:00 -0700) are available in the Git repository at: https://github.com/sophgo/linux.git tags/riscv-sophgo-dt-for-v7.2 for you to fetch changes up to 903a9364e40563faf4730dc63ad7446246f494ff: riscv: dts: sophgo: reduce SG2042 MSI count to 16 (2026-06-03 10:09:38 +0800) ---------------------------------------------------------------- RISC-V Devicetrees for v7.2 Sophgo: For CV18xx serials: - Add bindings for Milk-V "Duo S" board. For SG2042: - The CPU unit address incorrectly used decimal numbers, especially for those nodes which value >= 10. Now corrected to use hexadecimal. - The MSI controller actually only supports 16 interrupts; corrected to match the actual situation. - PCIe RCs are cache-coherent with the CPU. Marked it out for RC nodes. For SG2044: - The same as SG2042, use hex for CPU unit address. In additional, update Chen Wang's email address for Sopgho SoC maintainer. Signed-off-by: Chen Wang <[email protected]> ---------------------------------------------------------------- Chen Wang (1): MAINTAINERS: update Chen Wang's email address Han Gao (1): riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers Icenowy Zheng (1): riscv: dts: sophgo: reduce SG2042 MSI count to 16 Inochi Amaoto (2): riscv: dts: sophgo: sg2044: use hex for CPU unit address riscv: dts: sophgo: sg2042: use hex for CPU unit address Joshua Milas (2): dt-bindings: soc: sophgo: add Milk-V Duo S board compatibles dt-bindings: soc: sophgo: add sg2000 plic and clint documentation .../interrupt-controller/sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/soc/sophgo/sophgo.yaml | 4 + .../devicetree/bindings/timer/sifive,clint.yaml | 1 + MAINTAINERS | 2 +- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++----------- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 6 +- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++----------- 7 files changed, 248 insertions(+), 238 deletions(-)