Re: [PATCH v3 2/3] riscv: dts: sophgo: cv180x: Add PWR_GPIO controller

> You should follow the device address order. not by the device name.

Right, I placed it next to the other GPIO nodes by type. Will move it
to the correct position by unit address in v4.

Inochi Amaoto <[email protected]> =E6=96=BC 2026=E5=B9=B47=E6=9C=8813=E6=
=97=A5=E9=80=B1=E4=B8=80 =E4=B8=8A=E5=8D=888:57=E5=AF=AB=E9=81=93=EF=BC=9A
>
> On Fri, Jul 10, 2026 at 03:59:16PM +0800, Chen-Yu Yeh wrote:
> > The CV180x/CV181x family has an additional DesignWare APB GPIO
> > controller (PWR_GPIO) located in the always-on power domain at
> > 0x5021000. Add the node so that boards can reference GPIOs in this
> > bank, such as status LEDs.
> >
> > Signed-off-by: Chen-Yu Yeh <[email protected]>
> > ---
> > The base address and interrupt number match the vendor SDK device
> > tree (cv181x_base_riscv.dtsi: gpio@05021000, PLIC interrupt 70,
> > i.e. SOC_PERIPHERAL_IRQ(54)). Verified on Milk-V Duo 256M hardware
> > via the onboard status LED on porte 2.
> >
> >  arch/riscv/boot/dts/sophgo/cv180x.dtsi | 18 ++++++++++++++++++
> >  1 file changed, 18 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/d=
ts/sophgo/cv180x.dtsi
> > index 06b0ce5a2db7..25ad2bd265d7 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> > @@ -160,6 +160,24 @@ portd: gpio-controller@0 {
> >                       };
> >               };
> >
> > +             gpio4: gpio@5021000 {
> > +                     compatible =3D "snps,dw-apb-gpio";
> > +                     reg =3D <0x5021000 0x1000>;
> > +                     #address-cells =3D <1>;
> > +                     #size-cells =3D <0>;
> > +
> > +                     porte: gpio-controller@0 {
> > +                             compatible =3D "snps,dw-apb-gpio-port";
> > +                             gpio-controller;
> > +                             #gpio-cells =3D <2>;
> > +                             ngpios =3D <32>;
> > +                             reg =3D <0>;
> > +                             interrupt-controller;
> > +                             #interrupt-cells =3D <2>;
> > +                             interrupts =3D <SOC_PERIPHERAL_IRQ(54) IR=
Q_TYPE_LEVEL_HIGH>;
> > +                     };
> > +             };
> > +
>
> You should follow the device address order. not by the device name.
>
> >               saradc: adc@30f0000 {
> >                       compatible =3D "sophgo,cv1800b-saradc";
> >                       reg =3D <0x030f0000 0x1000>;
> > --
> > 2.43.0
> >