[PATCH v3 12/16] PCI: dwc: sophgo: Use cached PCIe capability offset
Hans Zhang <[email protected]> Mon, 20 Jul 2026 23:06:15 +0800
| Newsgroups | dev.linux.lists.sophgo,dev.linux.lists.imx,dev.linux.lists.spacemit,org.infradead.lists.linux-amlogic,org.infradead.lists.linux-riscv,org.infradead.lists.linux-rockchip,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci,org.kernel.vger.linux-tegra,org.ozlabs.lists.linuxppc-dev |
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| Message-ID | <[email protected]> |
dw_pcie_host_init() calls .init before caching, so we must call dw_pcie_get_pcie_cap() inside .init. The hardware is already enabled by the driver's own initialization before this point. The helper will cache the offset and avoid redundant searches. Signed-off-by: Hans Zhang <[email protected]> --- In pcie-sophgo, the call chain is: static const struct dw_pcie_host_ops sophgo_pcie_host_ops = { .init = sophgo_pcie_host_init, }; sophgo_pcie_host_init() -> sophgo_pcie_disable_l0s_l1() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-sophgo.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-sophgo.c b/drivers/pci/controller/dwc/pcie-sophgo.c index 044088898819..39703d2b7b5f 100644 --- a/drivers/pci/controller/dwc/pcie-sophgo.c +++ b/drivers/pci/controller/dwc/pcie-sophgo.c @@ -164,9 +164,10 @@ static void sophgo_pcie_msi_enable(struct dw_pcie_rp *pp) static void sophgo_pcie_disable_l0s_l1(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - u32 offset, val; + u8 offset; + u32 val; - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset = dw_pcie_get_pcie_cap(pci); dw_pcie_dbi_ro_wr_en(pci); -- 2.34.1