[PATCH v3 09/16] PCI: dwc: intel-gw: Use cached PCIe capability offset
Hans Zhang <[email protected]> Mon, 20 Jul 2026 23:06:12 +0800
| Newsgroups | dev.linux.lists.sophgo,dev.linux.lists.imx,dev.linux.lists.spacemit,org.infradead.lists.linux-amlogic,org.infradead.lists.linux-riscv,org.infradead.lists.linux-rockchip,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci,org.kernel.vger.linux-tegra,org.ozlabs.lists.linuxppc-dev |
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| Message-ID | <[email protected]> |
dw_pcie_host_init() calls .init before caching the offset, so inside .init we must call dw_pcie_get_pcie_cap() to obtain the offset (hardware is already enabled). The helper will cache the result for later use. Signed-off-by: Hans Zhang <[email protected]> --- In pcie-intel-gw, the call chain is: static const struct dw_pcie_host_ops intel_pcie_dw_ops = { .init = intel_pcie_rc_init, }; intel_pcie_rc_init() -> intel_pcie_host_setup() -> intel_pcie_link_setup() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-intel-gw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c index 348e579e683f..a891c3f8eb01 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -119,7 +119,7 @@ static void intel_pcie_ltssm_disable(struct intel_pcie *pcie) static void intel_pcie_link_setup(struct intel_pcie *pcie) { u32 val; - u8 offset = dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); + u8 offset = dw_pcie_get_pcie_cap(&pcie->pci); val = pcie_rc_cfg_rd(pcie, offset + PCI_EXP_LNKCTL); -- 2.34.1