Re: [PATCH v5 05/17] riscv: Add Zicclsm to cpufeature and hwprobe
Paul Walmsley <[email protected]>
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On Wed, 1 Jul 2026, Guodong Xu wrote: > From: Jesse Taube <[email protected]> > > Zicclsm requires misaligned support for all regular load and store > instructions, both scalar and vector, but not AMOs or other > specialized forms of memory access, to main memory regions with both > the cacheability and coherence PMAs, as defined in the profiles spec. > Even though mandated, misaligned loads and stores might execute > extremely slowly. Standard software distributions should assume their > existence only for correctness, not for performance. > > Reviewed-by: Conor Dooley <[email protected]> > Reviewed-by: Andy Chiu <[email protected]> > Reviewed-by: Charlie Jenkins <[email protected]> > Tested-by: Charlie Jenkins <[email protected]> > Signed-off-by: Jesse Taube <[email protected]> > [Rebased, rewrote doc text, minor commit message revisions] > Signed-off-by: Andrew Jones <[email protected]> > Signed-off-by: Guodong Xu <[email protected]> Thanks, queued for v7.3. - Paul