Re: [PATCH v2 4/5] dt-bindings: PCI: spacemit: Introduce Spacemit K3 PCIe host controller

On Sun, May 17, 2026 at 09:48:39AM +0800, Inochi Amaoto wrote:
> Add binding support for the PCIe controller on the SpacemiT K3 SoC.
> This controller is almost a standard Synopsys DesignWare PCIe IP,
> with some extra link and reset state control.
> 
> Signed-off-by: Inochi Amaoto <[email protected]>

Why can't you reuse the existing spacemit,k1-pcie-host.yaml binding? I see very
few differences which could be added using conditionals. Also, this binding
defines the PHY property in the controller node, which is a way backwards as we
now prefer to define these in Root Port node as spacemit,k1-pcie-host.yaml does.

- Mani

> ---
>  .../bindings/pci/spacemit,k3-pcie-host.yaml   | 135 ++++++++++++++++++
>  1 file changed, 135 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml
> new file mode 100644
> index 000000000000..46147a37a9ce
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml
> @@ -0,0 +1,135 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/spacemit,k3-pcie-host.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SpacemiT K3 PCI Express Host Controller
> +
> +maintainers:
> +  - Inochi Amaoto <[email protected]>
> +
> +description:
> +  The SpacemiT K3 SoC PCIe host controller is based on the Synopsys
> +  DesignWare PCIe IP. The controller uses the external MSI interrupt
> +  controller.
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-host-bridge.yaml#
> +  - $ref: /schemas/pci/snps,dw-pcie.yaml#
> +
> +properties:
> +  compatible:
> +    const: spacemit,k3-pcie
> +
> +  reg:
> +    items:
> +      - description: DesignWare PCIe registers
> +      - description: Data Bus Interface (DBI) shadow registers
> +      - description: ATU address space
> +      - description: PCIe configuration space
> +      - description: Link control registers
> +
> +  reg-names:
> +    items:
> +      - const: dbi
> +      - const: dbi2
> +      - const: atu
> +      - const: config
> +      - const: link
> +
> +  clocks:
> +    items:
> +      - description: DWC PCIe Data Bus Interface (DBI) clock
> +      - description: DWC PCIe application AXI-bus master interface clock
> +      - description: DWC PCIe application AXI-bus slave interface clock
> +
> +  clock-names:
> +    items:
> +      - const: dbi
> +      - const: mstr
> +      - const: slv
> +
> +  resets:
> +    items:
> +      - description: DWC PCIe Data Bus Interface (DBI) reset
> +      - description: DWC PCIe application AXI-bus master interface reset
> +      - description: DWC PCIe application AXI-bus slave interface reset
> +
> +  reset-names:
> +    items:
> +      - const: dbi
> +      - const: mstr
> +      - const: slv
> +
> +  msi-parent: true
> +
> +  phys:
> +    description:
> +      PHY phandle from the Combo PHY, the lane number does not depends
> +      on this, since the number of lanes provided by Combo PHY can be
> +      1 or 2.
> +    minItems: 1
> +    maxItems: 6
> +
> +  phy-names:
> +    minItems: 1
> +    maxItems: 6
> +
> +  spacemit,apmu:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    description:
> +      A phandle that refers to the APMU system controller, whose regmap is
> +      used in managing resets and link state, along with and offset of its
> +      reset control register.
> +    items:
> +      - items:
> +          - description: phandle to APMU system controller
> +          - description: register offset
> +
> +required:
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - msi-parent
> +  - spacemit,apmu
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    soc {
> +      #address-cells = <2>;
> +      #size-cells = <2>;
> +
> +      pcie@80000000 {
> +        compatible = "spacemit,k3-pcie";
> +        reg = <0x0  0x80000000 0x0 0x00001000>,
> +              <0x0  0x80100000 0x0 0x00001000>,
> +              <0x0  0x80300000 0x0 0x00003f20>,
> +              <0x11 0x00000000 0x0 0x00010000>,
> +              <0x0  0x82900000 0x0 0x00001000>;
> +        reg-names = "dbi", "dbi2", "atu", "config", "link";
> +        device_type = "pci";
> +        #address-cells = <3>;
> +        #size-cells = <2>;
> +        clocks = <&syscon_apmu 89>,
> +                 <&syscon_apmu 56>,
> +                 <&syscon_apmu 57>;
> +        clock-names = "dbi", "mstr", "slv";
> +        msi-parent = <&simsic>;
> +        ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>,
> +                 <0x02000000 0x0  0x00110000 0x11 0x00110000 0x0 0x7fef0000>,
> +                 <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>;
> +        resets = <&syscon_apmu 76>,
> +                 <&syscon_apmu 78>,
> +                 <&syscon_apmu 77>;
> +        reset-names = "dbi", "mstr", "slv";
> +        linux,pci-domain = <0>;
> +        spacemit,apmu = <&syscon_apmu 0x1f0>;
> +      };
> +    };
> +
> -- 
> 2.54.0
> 

-- 
மணிவண்ணன் சதாசிவம்