Re: [PATCH] platform: generic: spacemit: k1: fix wrong address definitions

On Tue, Jun 23, 2026 at 8:20 AM Junhui Liu <[email protected]> wrote:
>
> PMU_AP_CORE2_IDLE_CFG and PMU_AP_CORE3_IDLE_CFG are not continuous with
> PMU_AP_CORE0_IDLE_CFG and PMU_AP_CORE1_IDLE_CFG. They are at PMU AP
> base + 0x160 and + 0x164, matching the vendor OpenSBI definitions. After
> fixing these addresses, the intermediate cluster offset macros are
> redundant now, so define the wakeup and idle registers directly as
> PMU_AP_BASE offsets. This makes the actual register addresses easier to
> inspect and compare against the vendor code.
>
> C1_RVBADDR_HI_ADDR is also corrected according to the vendor OpenSBI
> definition. This was tested by writing an invalid value to the corrected
> address, which prevents cluster1 CPUs from coming online, while doing
> the same with the old address does not affect SMP boot.
>
> Fixes: 1f84ec2a ("platform: generic: spacemit: add K1")
> Signed-off-by: Junhui Liu <[email protected]>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  platform/generic/include/spacemit/k1.h | 46 +++++++++++++---------------------
>  1 file changed, 18 insertions(+), 28 deletions(-)
>
> diff --git a/platform/generic/include/spacemit/k1.h b/platform/generic/include/spacemit/k1.h
> index bd666346..7095bc08 100644
> --- a/platform/generic/include/spacemit/k1.h
> +++ b/platform/generic/include/spacemit/k1.h
> @@ -25,33 +25,23 @@
>
>  #define PMU_AP_BASE                            0xd4282800
>
> -#define PMU_AP_CORE0_WAKEUP_OFFSET             (PMU_AP_BASE + 0x12c)
> -#define PMU_AP_CORE4_WAKEUP_OFFSET             (PMU_AP_BASE + 0x324)
> -#define PMU_AP_CLUSTER0_WAKEUP_OFFSET(index)   (PMU_AP_CORE0_WAKEUP_OFFSET + index * 4)
> -#define PMU_AP_CLUSTER1_WAKEUP_OFFSET(index)   (PMU_AP_CORE4_WAKEUP_OFFSET + index * 4)
> -
> -#define PMU_AP_CORE0_IDLE_CFG_OFFSET           (PMU_AP_BASE + 0x124)
> -#define PMU_AP_CORE4_IDLE_CFG_OFFSET           (PMU_AP_BASE + 0x304)
> -#define PMU_AP_CLUSTER0_IDLE_CFG_OFFSET(index) (PMU_AP_CORE0_IDLE_CFG_OFFSET + index * 4)
> -#define PMU_AP_CLUSTER1_IDLE_CFG_OFFSET(index) (PMU_AP_CORE4_IDLE_CFG_OFFSET + index * 4)
> -
> -#define PMU_AP_CORE0_WAKEUP                    PMU_AP_CLUSTER0_WAKEUP_OFFSET(0)
> -#define PMU_AP_CORE1_WAKEUP                    PMU_AP_CLUSTER0_WAKEUP_OFFSET(1)
> -#define PMU_AP_CORE2_WAKEUP                    PMU_AP_CLUSTER0_WAKEUP_OFFSET(2)
> -#define PMU_AP_CORE3_WAKEUP                    PMU_AP_CLUSTER0_WAKEUP_OFFSET(3)
> -#define PMU_AP_CORE4_WAKEUP                    PMU_AP_CLUSTER1_WAKEUP_OFFSET(0)
> -#define PMU_AP_CORE5_WAKEUP                    PMU_AP_CLUSTER1_WAKEUP_OFFSET(1)
> -#define PMU_AP_CORE6_WAKEUP                    PMU_AP_CLUSTER1_WAKEUP_OFFSET(2)
> -#define PMU_AP_CORE7_WAKEUP                    PMU_AP_CLUSTER1_WAKEUP_OFFSET(3)
> -
> -#define PMU_AP_CORE0_IDLE_CFG                  PMU_AP_CLUSTER0_IDLE_CFG_OFFSET(0)
> -#define PMU_AP_CORE1_IDLE_CFG                  PMU_AP_CLUSTER0_IDLE_CFG_OFFSET(1)
> -#define PMU_AP_CORE2_IDLE_CFG                  PMU_AP_CLUSTER0_IDLE_CFG_OFFSET(2)
> -#define PMU_AP_CORE3_IDLE_CFG                  PMU_AP_CLUSTER0_IDLE_CFG_OFFSET(3)
> -#define PMU_AP_CORE4_IDLE_CFG                  PMU_AP_CLUSTER1_IDLE_CFG_OFFSET(0)
> -#define PMU_AP_CORE5_IDLE_CFG                  PMU_AP_CLUSTER1_IDLE_CFG_OFFSET(1)
> -#define PMU_AP_CORE6_IDLE_CFG                  PMU_AP_CLUSTER1_IDLE_CFG_OFFSET(2)
> -#define PMU_AP_CORE7_IDLE_CFG                  PMU_AP_CLUSTER1_IDLE_CFG_OFFSET(3)
> +#define PMU_AP_CORE0_WAKEUP                    (PMU_AP_BASE + 0x12c)
> +#define PMU_AP_CORE1_WAKEUP                    (PMU_AP_BASE + 0x130)
> +#define PMU_AP_CORE2_WAKEUP                    (PMU_AP_BASE + 0x134)
> +#define PMU_AP_CORE3_WAKEUP                    (PMU_AP_BASE + 0x138)
> +#define PMU_AP_CORE4_WAKEUP                    (PMU_AP_BASE + 0x324)
> +#define PMU_AP_CORE5_WAKEUP                    (PMU_AP_BASE + 0x328)
> +#define PMU_AP_CORE6_WAKEUP                    (PMU_AP_BASE + 0x32c)
> +#define PMU_AP_CORE7_WAKEUP                    (PMU_AP_BASE + 0x330)
> +
> +#define PMU_AP_CORE0_IDLE_CFG                  (PMU_AP_BASE + 0x124)
> +#define PMU_AP_CORE1_IDLE_CFG                  (PMU_AP_BASE + 0x128)
> +#define PMU_AP_CORE2_IDLE_CFG                  (PMU_AP_BASE + 0x160)
> +#define PMU_AP_CORE3_IDLE_CFG                  (PMU_AP_BASE + 0x164)
> +#define PMU_AP_CORE4_IDLE_CFG                  (PMU_AP_BASE + 0x304)
> +#define PMU_AP_CORE5_IDLE_CFG                  (PMU_AP_BASE + 0x308)
> +#define PMU_AP_CORE6_IDLE_CFG                  (PMU_AP_BASE + 0x30c)
> +#define PMU_AP_CORE7_IDLE_CFG                  (PMU_AP_BASE + 0x310)
>
>  /* power down */
>  #define PMU_AP_IDLE_PWRDWN                     BIT(0)
> @@ -68,7 +58,7 @@
>  #define C0_RVBADDR_LO_ADDR                     0xd4282db0
>  #define C0_RVBADDR_HI_ADDR                     0xd4282db4
>  #define C1_RVBADDR_LO_ADDR                     0xd4282eb0
> -#define C1_RVBADDR_HI_ADDR                     0xd4282c04
> +#define C1_RVBADDR_HI_ADDR                     0xd4282eb4
>
>  #define CCI_550_PLATFORM_CCI_ADDR              0xd8500000
>
>
> ---
> base-commit: a8be5e9478be08f09a720f7013ec30d6e2bd9fcc
> change-id: 20260605-k1-fix-addr-e25f6231cfb1
>
> Best regards,
> --
> Junhui Liu <[email protected]>
>
>
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