Re: [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters

On Sun, Aug 16, 2026 at 4:40 PM Yixun Lan <[email protected]> wrote:
>
> hi Guo,
>
> On 07:41 Sun 16 Aug     , Guo Ren wrote:
> > From: "GUO Ren (XuanTie)" <[email protected]>
> >
> > The initial K3 device tree used generic/placeholder values for the
> > IMSIC guest configuration:
> >
> >   riscv,guest-index-bits = <6>;
> >   riscv,num-guest-ids    = <511>;
> >
> > According to the SpacemiT K3 User Manual [1] these values are
> > incorrect for the X100 cores:
> >
> >  - Hypervisor Extension: RVH 1.0, GEILEN = 8
> >  - Advanced Interrupt Architecture (AIA):
> >     - M-mode MSI: 512
> >     - S-mode MSI: 512
> >     - VS-mode MSI: 64
> >
> > Therefore:
> >
> > - S-mode IMSIC (simsic) only needs guest-index-bits = 3 (to cover
> >   GEILEN = 8) and num-guest-ids = 63.
> ..
> > - M-mode IMSIC (mimsic) does not implement guest interrupt files at
> >   all, so the guest-related properties must be omitted.
> >
> Cc Junhui
>
> There is already one fix for IMSIC [1], but it's actually too late to
> pick for v7.3 .. I'm not sure how best to handle this, would it possible
It's not for v7.3; we could merge it in the next window.
The mimsic part is a separate fix; we could do these separately.

> on your side to pick Junhui's patch and rework to combine them to
> send a V2? or I could pick his patch first ..

I would remove the mimsic part, but I won't include it in v2. Because
there is no update for the mimsic patch, v2 makes it confusing.

>
> https://lore.kernel.org/all/[email protected]/
>
> > Although the KVM AIA driver will re-detect the actual number of guest
> > interrupt files via hgeie and correct guest-index-bits at runtime, the
> > device tree should still describe the correct hardware parameters.
> >
> > Update the device tree to match the silicon.
> >
> ..
> > [1] https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone/k3/k3_docs/k3_usermanual/08_cpu.md
> >
> no blank line and use "Link: https://.. [1]" format
>
> > Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC")
> > Cc: [email protected]
> > Cc: Guodong Xu <[email protected]>
> > Cc: Yixun Lan <[email protected]>
> > Signed-off-by: GUO Ren (XuanTie) <[email protected]>
> > ---
> >  arch/riscv/boot/dts/spacemit/k3.dtsi | 6 ++----
> >  1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > index 19fc9b49668e..4120eb0c4083 100644
> > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > @@ -1127,9 +1127,9 @@ simsic: interrupt-controller@e0400000 {
> >                                             <&cpu4_intc 9>, <&cpu5_intc 9>,
> >                                             <&cpu6_intc 9>, <&cpu7_intc 9>;
> >                       msi-controller;
> > -                     riscv,guest-index-bits = <6>;
> > +                     riscv,guest-index-bits = <3>;
> >                       riscv,hart-index-bits = <4>;
> > -                     riscv,num-guest-ids = <511>;
> > +                     riscv,num-guest-ids = <63>;
> >                       riscv,num-ids = <511>;
> >               };
> >
> > @@ -1168,9 +1168,7 @@ mimsic: interrupt-controller@f1000000 {
> >                                             <&cpu4_intc 11>, <&cpu5_intc 11>,
> >                                             <&cpu6_intc 11>, <&cpu7_intc 11>;
> >                       msi-controller;
> > -                     riscv,guest-index-bits = <6>;
> >                       riscv,hart-index-bits = <4>;
> > -                     riscv,num-guest-ids = <511>;
> >                       riscv,num-ids = <511>;
> >                       status = "reserved";
> >               };
> > --
> > 2.43.0
> >
>
> --
> Yixun Lan (dlan)



-- 
Best Regards
 Guo Ren