[PATCH V2] riscv: dts: spacemit: k3: fix IMSIC num-guest-ids

From: "GUO Ren (XuanTie)" <[email protected]>

The initial K3 device tree used generic/placeholder values for the
IMSIC guest configuration:

  riscv,num-guest-ids    = <511>;

According to the SpacemiT K3 User Manual this values is incorrect
for the X100 cores:

 - Advanced Interrupt Architecture (AIA):
    - M-mode MSI: 512
    - S-mode MSI: 512
    - VS-mode MSI: 64

Therefore, S-mode IMSIC (simsic) needs num-guest-ids = 63.

Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC")
Cc: [email protected]
Cc: Guodong Xu <[email protected]>
Cc: Yixun Lan <[email protected]>
Signed-off-by: GUO Ren (XuanTie) <[email protected]>
---
V2:
 - Drop the riscv,guest-index-bits change for simsic: the property
   describes the number of guest index bits in the MSI target address,
   and the per-hart stride on K3 is 0x40000 = 2^(6 + 12), so 6 is
   correct as is.
 - Drop the mimsic changes: already fixed by Junhui.
 - Reword the subject and commit log accordingly.
---
 arch/riscv/boot/dts/spacemit/k3.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 19fc9b49668e..4a4a9ec7c981 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -1129,7 +1129,7 @@ simsic: interrupt-controller@e0400000 {
 			msi-controller;
 			riscv,guest-index-bits = <6>;
 			riscv,hart-index-bits = <4>;
-			riscv,num-guest-ids = <511>;
+			riscv,num-guest-ids = <63>;
 			riscv,num-ids = <511>;
 		};
 
-- 
2.43.0