[PATCH v1 9/9] x86/cpuid: Rename native_cpuid_REG() to cpuid_native_REG()

In order to let all the APIs under <cpuid/api.h> have a shared "cpuid_"
namespace, rename native_cpuid_REG() to cpuid_native_REG().

To beetter align with the new namespace, also rename the internal
NATIVE_CPUID_REG() macro to __CPUID_NATIVE_REG().

Adjust all call-sites accordingly.

Suggested-by: Ingo Molnar <[email protected]>
Signed-off-by: Ahmed S. Darwish <[email protected]>
---
 arch/x86/boot/compressed/pgtable_64.c   |  4 ++--
 arch/x86/include/asm/cpuid/api.h        | 12 ++++++------
 arch/x86/include/asm/microcode.h        |  2 +-
 arch/x86/kernel/cpu/microcode/amd.c     |  2 +-
 arch/x86/kernel/cpu/microcode/core.c    |  6 +++---
 arch/x86/kernel/head32.c                |  2 +-
 drivers/firmware/efi/libstub/x86-5lvl.c |  4 ++--
 7 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
index d8c5de40669d..8cfe50988aa2 100644
--- a/arch/x86/boot/compressed/pgtable_64.c
+++ b/arch/x86/boot/compressed/pgtable_64.c
@@ -125,8 +125,8 @@ asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable)
 	 */
 	if (IS_ENABLED(CONFIG_X86_5LEVEL) &&
 			!cmdline_find_option_bool("no5lvl") &&
-			native_cpuid_eax(0) >= 7 &&
-			(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
+			cpuid_native_eax(0) >= 7 &&
+			(cpuid_native_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
 		l5_required = true;
 
 		/* Initialize variables for 5-level paging */
diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index 7f4644747649..9f8a1176ad86 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -35,8 +35,8 @@ static inline void cpuid_native(u32 *eax, u32 *ebx,
 	    : "memory");
 }
 
-#define NATIVE_CPUID_REG(reg)					\
-static inline u32 native_cpuid_##reg(u32 op)			\
+#define __CPUID_NATIVE_REG(reg)					\
+static inline u32 cpuid_native_##reg(u32 op)			\
 {								\
 	u32 eax = op, ebx, ecx = 0, edx;			\
 								\
@@ -48,10 +48,10 @@ static inline u32 native_cpuid_##reg(u32 op)			\
 /*
  * Native CPUID functions returning a single datum:
  */
-NATIVE_CPUID_REG(eax)
-NATIVE_CPUID_REG(ebx)
-NATIVE_CPUID_REG(ecx)
-NATIVE_CPUID_REG(edx)
+__CPUID_NATIVE_REG(eax)
+__CPUID_NATIVE_REG(ebx)
+__CPUID_NATIVE_REG(ecx)
+__CPUID_NATIVE_REG(edx)
 
 #ifdef CONFIG_PARAVIRT_XXL
 # include <asm/paravirt.h>
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 695e569159c1..755c9f693118 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -64,7 +64,7 @@ static inline u32 intel_get_microcode_revision(void)
 	native_wrmsrl(MSR_IA32_UCODE_REV, 0);
 
 	/* As documented in the SDM: Do a CPUID 1 here */
-	native_cpuid_eax(1);
+	cpuid_native_eax(1);
 
 	/* get the current revision from MSR 0x8B */
 	native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index 4a10d35e70aa..d757383b653c 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -1098,7 +1098,7 @@ static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t siz
 
 static int __init save_microcode_in_initrd(void)
 {
-	unsigned int cpuid_1_eax = native_cpuid_eax(1);
+	unsigned int cpuid_1_eax = cpuid_native_eax(1);
 	struct cpuinfo_x86 *c = &boot_cpu_data;
 	struct cont_desc desc = { 0 };
 	enum ucode_state ret;
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index 1395fa72960f..9924b8238492 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -106,7 +106,7 @@ static bool __init check_loader_disabled_bsp(void)
 	 * completely accurate as xen pv guests don't see that CPUID bit set but
 	 * that's good enough as they don't land on the BSP path anyway.
 	 */
-	if (native_cpuid_ecx(1) & BIT(31))
+	if (cpuid_native_ecx(1) & BIT(31))
 		return true;
 
 	if (x86_cpuid_vendor() == X86_VENDOR_AMD) {
@@ -128,7 +128,7 @@ void __init load_ucode_bsp(void)
 	if (!cpuid_feature())
 		return;
 
-	cpuid_1_eax = native_cpuid_eax(1);
+	cpuid_1_eax = cpuid_native_eax(1);
 
 	switch (x86_cpuid_vendor()) {
 	case X86_VENDOR_INTEL:
@@ -162,7 +162,7 @@ void load_ucode_ap(void)
 	if (dis_ucode_ldr)
 		return;
 
-	cpuid_1_eax = native_cpuid_eax(1);
+	cpuid_1_eax = cpuid_native_eax(1);
 
 	switch (x86_cpuid_vendor()) {
 	case X86_VENDOR_INTEL:
diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c
index de001b2146ab..43aa1cfc1b65 100644
--- a/arch/x86/kernel/head32.c
+++ b/arch/x86/kernel/head32.c
@@ -146,7 +146,7 @@ void __init __no_stack_protector mk_early_pgtbl_32(void)
 
 #ifdef CONFIG_MICROCODE_INITRD32
 	/* Running on a hypervisor? */
-	if (native_cpuid_ecx(1) & BIT(31))
+	if (cpuid_native_ecx(1) & BIT(31))
 		return;
 
 	params = (struct boot_params *)__pa_nodebug(&boot_params);
diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi/libstub/x86-5lvl.c
index 77359e802181..db347c91edb3 100644
--- a/drivers/firmware/efi/libstub/x86-5lvl.c
+++ b/drivers/firmware/efi/libstub/x86-5lvl.c
@@ -34,8 +34,8 @@ efi_status_t efi_setup_5level_paging(void)
 		return EFI_SUCCESS;
 
 	/* check for 5 level paging support */
-	if (native_cpuid_eax(0) < 7 ||
-	    !(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))
+	if (cpuid_native_eax(0) < 7 ||
+	    !(cpuid_native_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))
 		return EFI_SUCCESS;
 
 	/* allocate some 32-bit addressable memory for code and a page table */
-- 
2.49.0