Re: [PATCH linux-evl v2 0/2] Add RISC-V support to EVL
Tobias Schaffner <[email protected]>
| Newsgroups | dev.linux.lists.xenomai |
|---|---|
| Message-ID | <[email protected]> |
Hi all! Some additional notes on this patch set: This has been tested together with the underlying v5 version of the RISC-V Dovetail patches in QEMU, as well as on the StarFive VisionFive 2 board. These tests were done in my home lab, but I plan to integrate one of my boards into the Xenomai-images lab next week. All tests of the evl testsuite pass besides the ptrace-sync test. See the mail "evl: ptrace continue without hardware singlestepping support" from 19th of February on this open issue. Please find the results of the latency tests attached. * All tests were done with two isolated cores. * The tests show one latmus thread per core (isolated and system cores), started with "latmus -m --user -p 200 -P 99 -c 0". * In the stressed version, stressing was done with "stress-ng --procfs 1 --null 1 --getdent 1 --sock 1 --cpu 1 --vm 1 --vm-bytes 64M --timer 1 --hrtimers 1 --switch 1 --fp 1". While testing different background loads, I noticed that stressing virtual memory and the MMC at the same time leads to high latency spikes. The memlat-correlation.png shows a correlation between concurrent memory access latency and latmus latency measurements while stressing the system in this way. The results indicate that the latencies occur when the measurement thread is evicted from the cache and competes with the MMC for the DDR controller. While I can only observe this with targeted stressing, this hardware limitation should be kept in mind. Thanks to Philippe, Jan and Florian for answering all my questions and the guidance at this point. :) Best, Tobias On 3/20/26 22:41, Tobias Schaffner wrote: > Hi all, > > this series introduces an initial EVL port for RISC-V. > > While some tests are still failing, I’d like to share this early > version with the community to gather feedback, reviews, and hopefully > some assistance in refining the port. > > The patches have been tested in combination with the Dovetail RISC-V > port on top of v7.0-evl-rebase. > > Looking forward to your feedback and suggestions. > > Changes since v1: > * rebase to v7.0-evl-rebase > * add missing guards for building without evl > > Best, > Tobias > > Tobias Schaffner (1): > riscv: Add EVL core > > shannmu (1): > riscv: Add FPU register test support > > arch/riscv/Kconfig | 2 + > arch/riscv/include/asm/evl/calibration.h | 12 ++ > arch/riscv/include/asm/evl/fptest.h | 31 +++++ > arch/riscv/include/asm/evl/syscall.h | 25 ++++ > arch/riscv/include/asm/evl/thread.h | 12 ++ > arch/riscv/include/dovetail/irq.h | 11 ++ > arch/riscv/include/dovetail/mm_info.h | 11 ++ > arch/riscv/include/dovetail/net.h | 11 ++ > arch/riscv/include/dovetail/netdevice.h | 11 ++ > arch/riscv/include/dovetail/poll.h | 11 ++ > arch/riscv/include/dovetail/skbuff.h | 11 ++ > arch/riscv/include/dovetail/thread_info.h | 11 ++ > arch/riscv/include/uapi/asm/evl/fptest.h | 138 ++++++++++++++++++++++ > 13 files changed, 297 insertions(+) > create mode 100644 arch/riscv/include/asm/evl/calibration.h > create mode 100644 arch/riscv/include/asm/evl/fptest.h > create mode 100644 arch/riscv/include/asm/evl/syscall.h > create mode 100644 arch/riscv/include/asm/evl/thread.h > create mode 100644 arch/riscv/include/dovetail/irq.h > create mode 100644 arch/riscv/include/dovetail/mm_info.h > create mode 100644 arch/riscv/include/dovetail/net.h > create mode 100644 arch/riscv/include/dovetail/netdevice.h > create mode 100644 arch/riscv/include/dovetail/poll.h > create mode 100644 arch/riscv/include/dovetail/skbuff.h > create mode 100644 arch/riscv/include/dovetail/thread_info.h > create mode 100644 arch/riscv/include/uapi/asm/evl/fptest.h >
starfive-visionfive2-idle.hist
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starfive-visionfive2-stressed.hist
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starfive-visionfive2-idle.png
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memlat-correlation.png
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