Re: [PATCH dovetail v5 00/12] riscv: Add dovetail support
Jan Kiszka <[email protected]>
| Newsgroups | dev.linux.lists.xenomai |
|---|---|
| Message-ID | <[email protected]> |
On 23.03.26 16:53, Bjorn Helgaas wrote: > [+cc Thomas, irqchip driver maintainer, series at > https://lore.kernel.org/all/[email protected]] > > On Fri, Mar 20, 2026 at 10:36:45PM +0100, Tobias Schaffner wrote: >> Hi all, >> >> this series introduces initial support for Dovetail on RISC-V. > > 02/12 mentions "the Dovetail/IRQ pipeline model used on other > architectures," but my quick grep for dovetail and IRQ pipelining > didn't find anything. > These patches are not targeting the upstream kernel. I wonder how you got aware of them as I only see the Xenomai list in CC. Jan >> Feedback, suggestions, and especially reviews are very welcome. >> >> Changes since v1: >> * Disable independent irq/softirq stack usage when pipelining >> * Drop KVM changes as long as they can not be properly tested >> >> Changes since v2: >> * Rework trap handling >> >> Changes since v3: >> * Included the IRQ pipelining patches to have all riscv specific >> patches included >> * Rebased to dovetail/v6.18.y-dovetail-rebase >> * Merged most of the fixes >> * Fixed IRQ Stack handling and enabled IRQ_STACKS again >> >> Changes since v4: >> * Rebased to dovetail/v7.0.y-dovetail-rebase >> * Applied suggestions from the last patch set >> * Added starfive-visionfive2 board support >> * Introduced raw console device based on sbi debug console >> * Reworked pipelined irq handling >> >> Best, >> Tobias >> >> Tobias Schaffner (12): >> riscv: introduce raw console device >> riscv: irq_pipeline: add IRQ pipelining core >> riscv: irq_pipeline: enable hard IRQs during in-band trap handling >> irqchip/riscv-aplic-direct: enable pipelined interrupt control >> irqchip/irq-riscv-aplic-msi: enable pipelined interrupt control >> irqchip/irq-riscv-imsic-platform: enable pipelined interrupt control >> irqchip/irq-riscv-intc: enable pipelined interrupt control >> irqchip/irq-sifive-plic: enable pipelined interrupt control >> clocksource/timer-riscv: irq_pipeline: enable pipelined clock events >> pinctrl: starfive: irq_pipeline: enable pipelined interrupt control >> pci: plda: irq_pipeline: enable pipelined interrupt control >> riscv: dovetail: add core support >> >> arch/riscv/Kconfig | 3 + >> arch/riscv/include/asm/dovetail.h | 23 ++ >> arch/riscv/include/asm/irq_pipeline.h | 145 +++++++++++++ >> arch/riscv/include/asm/irqflags.h | 32 ++- >> arch/riscv/include/asm/mmu_context.h | 2 + >> arch/riscv/include/asm/smp.h | 7 + >> arch/riscv/include/asm/syscall.h | 6 + >> arch/riscv/include/asm/thread_info.h | 17 ++ >> arch/riscv/kernel/Makefile | 2 + >> arch/riscv/kernel/irq_pipeline.c | 26 +++ >> arch/riscv/kernel/kernel_mode_vector.c | 2 +- >> arch/riscv/kernel/raw_printk.c | 33 +++ >> arch/riscv/kernel/sbi-ipi.c | 12 +- >> arch/riscv/kernel/smp.c | 55 ++++- >> arch/riscv/kernel/smpboot.c | 2 +- >> arch/riscv/kernel/traps.c | 202 ++++++++++++++++-- >> arch/riscv/mm/cacheflush.c | 5 +- >> arch/riscv/mm/context.c | 20 +- >> arch/riscv/mm/fault.c | 29 ++- >> drivers/clocksource/timer-riscv.c | 11 +- >> drivers/irqchip/irq-riscv-aplic-direct.c | 3 +- >> drivers/irqchip/irq-riscv-aplic-msi.c | 3 +- >> drivers/irqchip/irq-riscv-imsic-platform.c | 4 +- >> drivers/irqchip/irq-riscv-intc.c | 2 + >> drivers/irqchip/irq-sifive-plic.c | 10 +- >> drivers/pci/controller/plda/pcie-plda-host.c | 2 + >> .../starfive/pinctrl-starfive-jh7110.c | 2 +- >> .../starfive/pinctrl-starfive-jh7110.h | 2 +- >> 28 files changed, 593 insertions(+), 69 deletions(-) >> create mode 100644 arch/riscv/include/asm/dovetail.h >> create mode 100644 arch/riscv/include/asm/irq_pipeline.h >> create mode 100644 arch/riscv/kernel/irq_pipeline.c >> create mode 100644 arch/riscv/kernel/raw_printk.c >> >> -- >> 2.43.0 >> -- Siemens AG, Foundational Technologies Linux Expert Center