[Buildroot] [git commit] package/gcc: 15.3.0: add GCC patch to fix mips/glibc build issue

commit: https://gitlab.com/buildroot.org/buildroot/-/commit/11bf0dc202c46c0cc3b9a5357b28fb649a886362
branch: https://gitlab.com/buildroot.org/buildroot/-/tree/master

Fixes a build error with glibc:

programs/locfile.c: In function 'align_locale_data':
programs/locfile.c:584:1: internal compiler error:
 in mips_load_store_insns, at config/mips/mips.cc:3137

by backporting an upstream fix which is already included in gcc 16.1.

The build error does not occur with gcc 14.x.

Fixes:
https://autobuild.buildroot.org/results/b925a444bb3ef03354224ac643b0b3160c4c5e8a/

The oldest recorded build error dates back to July 2025:
https://autobuild.buildroot.net/results/cb1/cb156fb938de26dd5dfe7fc48a1e061efa0284c7/

so a backport to LTS branches should be considered.

Signed-off-by: Bernd Kuhls <[email protected]>
Signed-off-by: Thomas Petazzoni <[email protected]>
---
 ...mization-123833-Use-of-insn-attributes-in.patch | 85 ++++++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/package/gcc/15.3.0/0003-PR-rtl-optimization-123833-Use-of-insn-attributes-in.patch b/package/gcc/15.3.0/0003-PR-rtl-optimization-123833-Use-of-insn-attributes-in.patch
new file mode 100644
index 0000000000..81b43a5757
--- /dev/null
+++ b/package/gcc/15.3.0/0003-PR-rtl-optimization-123833-Use-of-insn-attributes-in.patch
@@ -0,0 +1,85 @@
+From 654c733fa3f10531f3fd6b6d89e39f28c0075bd6 Mon Sep 17 00:00:00 2001
+From: Roger Sayle <[email protected]>
+Date: Sat, 7 Feb 2026 07:50:41 +0000
+Subject: [PATCH] PR rtl-optimization/123833: Use of insn attributes in
+ insn_costs corrupts recog_data.
+
+Thanks again to Jeff Law and Andrew Pinski.  Here's a revised patch that
+addresses the true underlying cause of PR 128333.  recog.cc's cancel_changes
+was not correctly updating the recog_data cache, which leads to strange
+(incorrect) behavior in fwprop and ifcvt.
+
+2026-02-07  Roger Sayle  <[email protected]>
+	    Andrew Pinski  <[email protected]>
+	    Jeff Law  <[email protected]>
+
+gcc/ChangeLog
+	PR rtl-optimization/123833
+	* recog.cc (cancel_changes): Update the recog_data cache if it
+	holds the instruction being changed.
+
+gcc/testsuite
+	PR rtl-optimization/123833
+	* gcc.target/mips/pr123833.c: New test case.
+
+Upstream: https://gcc.gnu.org/cgit/gcc/commit/?id=654c733fa3f10531f3fd6b6d89e39f28c0075bd6
+
+Signed-off-by: Bernd Kuhls <[email protected]>
+---
+ gcc/recog.cc                             |  6 +++++-
+ gcc/testsuite/gcc.target/mips/pr123833.c | 26 ++++++++++++++++++++++++
+ 2 files changed, 31 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/mips/pr123833.c
+
+diff --git a/gcc/recog.cc b/gcc/recog.cc
+index 48f6b45ec6d..f37e548d6ab 100644
+--- a/gcc/recog.cc
++++ b/gcc/recog.cc
+@@ -608,7 +608,11 @@ cancel_changes (int num)
+       else
+ 	*changes[i].loc = changes[i].old;
+       if (changes[i].object && !MEM_P (changes[i].object))
+-	INSN_CODE (changes[i].object) = changes[i].old_code;
++	{
++	  INSN_CODE (changes[i].object) = changes[i].old_code;
++	  if (recog_data.insn == changes[i].object)
++	    recog_data.insn = nullptr;
++	}
+     }
+   num_changes = num;
+ }
+diff --git a/gcc/testsuite/gcc.target/mips/pr123833.c b/gcc/testsuite/gcc.target/mips/pr123833.c
+new file mode 100644
+index 00000000000..4d0c9e8eaec
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/mips/pr123833.c
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-options "-O1 -mabi=64 -mhard-float" } */
++
++typedef short int16_t;
++typedef signed char int8_t;
++typedef long long int64_t;
++typedef unsigned char uint8_t;
++typedef unsigned long long uint64_t;
++
++#define BS_VEC(type, num) type __attribute__((vector_size(num * sizeof(type))))
++BS_VEC(int8_t, 2) backsmith_pure_0(int64_t);
++uint64_t backsmith_pure_4(int16_t BS_ARG_0)
++{
++    BS_VEC(int16_t, 16)
++    BS_VAR_0 = __builtin_convertvector(
++        __builtin_shufflevector(backsmith_pure_0(0), backsmith_pure_0(0), 0, 2,
++                                2, 3, 2, 1, 2, 3, 0, 2, 0, 0, 2, 2, 0, 1),
++        BS_VEC(int16_t, 16));
++    for (;;)
++    {
++        if (__builtin_ctzg((uint8_t)BS_VAR_0[3], BS_ARG_0))
++            for (;;);
++        return 0;
++    }
++}
++
+-- 
+2.47.3
+
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