Re: [PATCH] ASoC: rt1320-sdw: Add settings to support more base clock frequency

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On Thu, Jul 16, 2026 at 02:15:36PM +0800, [email protected] wrote:

> Add settings to support more base clock frequency on different platform.

> +static int rt1320_bus_config(struct sdw_slave *slave,
> +				struct sdw_bus_params *params)
> +{
> +	struct  rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev);
> +	unsigned int clk_base;
> +
> +	regmap_read(rt1320->regmap, 0x004d, &clk_base);

Do we need to set clock_reg_supported?

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Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmprQrAACgkQJNaLcl1U
h9BXhgf7BOaSx/dc7QVjpeMHBdYRmhN/HlivMiUTY/sPYSwqX7DxjnL91KJzMaPg
ZSjmq9pQ3u9xUY9NIgqHc+6VkLaZJkcib7CahuNGPzdOoOm+luGYRWEJcdG3PGl2
o3jyfxtnNCgc3nlia9JZPel0DlpAdVY8/qqTZESY98o+b1DbDSetC47dLXuzQICG
nc8QraCc0VNUPQ3Vav7nrwKDWX6NVAGkz7uDPLYItK0DrrrHX6kPm88EePIeJj7v
P5RqsZ8nZel1HcgyFRHi7TmSMTmgScxaayFzV+a5WKsaZ7qGJai9mKeiA6KeZmk1
UvVfBuD6ccgjreYqW3g8Ndip+0m7Hw==
=GCAE
-----END PGP SIGNATURE-----

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