Re: [PATCH 6.1.y-cip 13/32] spi: rzv2h-rspi: make transfer clock rate finding chip-specific

Hi!

> From: Cosmin Tanislav <[email protected]>
> 
> commit 77d931584dd38916b66c65320c80a65cbef4b122 upstream.
> 
> The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a more
> complicated clocking setup for the SPI transfer clock than RZ/V2H, as
> the clock from which it is generated supports multiple dividers.
> 
> To prepare for adding support for these SoCs, split out the logic for
> finding the SPR and BRDV for a fixed clock into
> rzv2h_rspi_find_rate_fixed(), and add and use a .find_tclk_rate()
> callback into the chip-specific structure.
> 
> Signed-off-by: Cosmin Tanislav <[email protected]>
> Link: https://patch.msgid.link/[email protected]
> Signed-off-by: Mark Brown <[email protected]>
> Signed-off-by: Tommaso Merciai <[email protected]>
> ---
>  drivers/spi/spi-rzv2h-rspi.c | 62 ++++++++++++++++++++++++++++++------
>  1 file changed, 53 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/spi/spi-rzv2h-rspi.c b/drivers/spi/spi-rzv2h-rspi.c
> index f22f418325d8..fc0957d2bb2a 100644
> --- a/drivers/spi/spi-rzv2h-rspi.c
> +++ b/drivers/spi/spi-rzv2h-rspi.c
> @@ -237,9 +248,13 @@ static inline u32 rzv2h_rspi_calc_bitrate(unsigned long tclk_rate, u8 spr,
>  	return DIV_ROUND_UP(tclk_rate, (2 * (spr + 1) * (1 << brdv)));
>  }
>  
> -static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz)
> +static void rzv2h_rspi_find_rate_fixed(struct clk *clk, u32 hz,
> +				       u8 spr_min, u8 spr_max,
> +				       struct rzv2h_rspi_best_clock *best)
>  {
> -	unsigned long tclk_rate;
> +	unsigned long clk_rate;
> +	unsigned long error;
> +	u32 actual_hz;
>  	int spr;
>  	u8 brdv;
>  
> @@ -252,21 +267,49 @@ static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz)
>  	 * * n = SPR - is RSPI_SPBR.SPR (from 0 to 255)
>  	 * * N = BRDV - is RSPI_SPCMD.BRDV (from 0 to 3)
>  	 */
> -	tclk_rate = clk_get_rate(rspi->tclk);
> +	clk_rate = clk_get_rate(clk);
>  	for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) {
> -		spr = DIV_ROUND_UP(tclk_rate, hz * (1 << (brdv + 1)));
> +		spr = DIV_ROUND_UP(clk_rate, hz * (1 << (brdv + 1)));
>  		spr--;
> -		if (spr >= RSPI_SPBR_SPR_MIN && spr <= RSPI_SPBR_SPR_MAX)
> +		if (spr >= spr_min && spr <= spr_max)
>  			goto clock_found;
>  	}
>  
> -	return 0;
> +	return;
>

So this is basically error return, yet we are returning void. Not nice.

> +static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz)
> +{
> +	struct rzv2h_rspi_best_clock best_clock = {
> +		.error = ULONG_MAX,
> +	};
> +
> +	rspi->info->find_tclk_rate(rspi->tclk, hz, RSPI_SPBR_SPR_MIN,
> +				   RSPI_SPBR_SPR_MAX, &best_clock);
> +
> +	if (!best_clock.clk_rate)
> +		return -EINVAL;

-errno in function returning u32. I see this is fixed in subsequent patches.

Best regards,
									Pavel

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