[PATCH 6.12.y-cip 21/39] clk: renesas: rzg2l: Drop always-false check in rzg3s_cpg_pll_clk_recalc_rate()
Biju <[email protected]>
| Newsgroups | org.cip-project.lists.cip-dev |
|---|---|
| Message-ID | <[email protected]> |
From: Biju Das <[email protected]> [ Upstream commit 79b5d6970b4e5b7b7ee4d7fdb18e950086b72bde ] Drop the unwanted check in rzg3s_cpg_pll_clk_recalc_rate() as the function is SoC-specific. Reviewed-by: Claudiu Beznea <[email protected]> Signed-off-by: Biju Das <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Biju Das <[email protected]> --- drivers/clk/renesas/rzg2l-cpg.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 5ced73696efa..ac49eb8b4a30 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1108,9 +1108,6 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw, u32 nir, nfr, mr, pr, val, setting; u64 rate; - if (pll_clk->type != CLK_TYPE_G3S_PLL) - return parent_rate; - setting = GET_REG_SAMPLL_SETTING(pll_clk->conf); if (setting) { val = readl(priv->base + setting); -- 2.43.0