[PATCH 6.12.y-cip 11/23] pinctrl: renesas: rzg2l: Update OEN pin validation to use exact match
Biju <[email protected]>
| Newsgroups | org.cip-project.lists.cip-dev |
|---|---|
| Message-ID | <[email protected]> |
From: Biju Das <[email protected]> [ Upstream commit da4a37540b780c386eb2362bfcc638f769918cb1 ] The RZ/G2L SoC uses pin 0 from a port for OEN while RZ/G3L uses pin 1. The existing greater-than comparison against oen_max_pin in rzg2l_pin_to_oen_bit() would incorrectly accept any pin below that value rather than enforcing the single valid OEN pin for each SoC. Replace the range check with an exact equality test so that only the designated OEN pin is accepted. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Biju Das <[email protected]> --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 9136cc352b9c..370ffb829287 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1126,7 +1126,7 @@ static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data); u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); - if (pin > pctrl->data->hwcfg->oen_max_pin) + if (pin != pctrl->data->hwcfg->oen_max_pin) return -EINVAL; /* -- 2.43.0