[PATCH 6.12.y-cip 19/23] arm64: dts: renesas: r9a08g046: Add pincontrol node
Biju <[email protected]>
| Newsgroups | org.cip-project.lists.cip-dev |
|---|---|
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From: Biju Das <[email protected]> [ Upstream commit ea82a68bb33691ea16188b6b9bef15cde874a193 ] Add pincontrol node to RZ/G3L ("R9A08G046") SoC DTSI and set the icu as the interrupt-parent of the pin controller to route GPIO interrupts through the IA55 interrupt controller. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Biju Das <[email protected]> --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 232a0e299df7..0cedf5a38291 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -204,10 +204,21 @@ sysc: system-controller@11020000 { }; pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a08g046-pinctrl"; reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; - /* placeholder */ + gpio-ranges = <&pinctrl 0 0 232>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu>; + clocks = <&cpg CPG_MOD R9A08G046_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_GPIO_RSTN>, + <&cpg R9A08G046_GPIO_PORT_RESETN>, + <&cpg R9A08G046_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; + renesas,clonech = <&sysc 0xe2c>; }; icu: interrupt-controller@11050000 { -- 2.43.0