[PATCH 6.12.y-cip 7/8] arm64: dts: renesas: r9a09g087: Add xSPI nodes
Lad Prabhakar <[email protected]> Mon, 6 Jul 2026 19:23:27 +0100
| Newsgroups | org.cip-project.lists.cip-dev |
|---|---|
| Message-ID | <[email protected]> |
commit 8fa0a1ae4f434be1b8ea6223636c065c8e39d09b upstream. Add device tree nodes for the two xSPI (Expanded SPI) controllers integrated into the RZ/N2H (R9A09G087) SoC. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Lad Prabhakar <[email protected]> --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index b1f6b997376f..64886ab95bc3 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -880,6 +880,46 @@ mii_conv3: mii-conv@3 { }; }; + xspi0: spi@801c0000 { + compatible = "renesas,r9a09g087-xspi", + "renesas,r9a09g047-xspi"; + reg = <0 0x801c0000 0 0x1000>, + <0 0x40000000 0 0x10000000>; + reg-names = "regs", "dirmap"; + interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pulse", "err_pulse"; + clocks = <&cpg CPG_MOD 4>, + <&cpg CPG_CORE R9A09G087_XSPI_CLK0>; + clock-names = "ahb", "spi"; + resets = <&cpg 4>; + reset-names = "hresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + xspi1: spi@801c1000 { + compatible = "renesas,r9a09g087-xspi", + "renesas,r9a09g047-xspi"; + reg = <0 0x801c1000 0 0x1000>, + <0 0x50000000 0 0x10000000>; + reg-names = "regs", "dirmap"; + interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pulse", "err_pulse"; + clocks = <&cpg CPG_MOD 5>, + <&cpg CPG_CORE R9A09G087_XSPI_CLK1>; + clock-names = "ahb", "spi"; + resets = <&cpg 5>; + reset-names = "hresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@80280000 { compatible = "renesas,r9a09g087-cpg-mssr"; reg = <0 0x80280000 0 0x1000>, -- 2.43.0