Re: [PATCH 6/9] drm/amdgpu/gfx7: Clean up gfx ring during reset

On 13/07/2026 13:58, Timur Kristóf wrote:
> Clear the WPTR and RPTR at ring initialization.
> Additionally clear the ring contents during reset.

Please add the why part to your commit messages. ;)

Cover letter mentions the series is reworking to match gfx7 to gfx8 but 
I looked in drm-tip and amd-staging-drm-next and 
gfx_v8_0_cp_gfx_resume() does not yet have these changes.

> Signed-off-by: Timur Kristóf <[email protected]>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index a93cc02c3400..915612628f9a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -2546,8 +2546,14 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
>   	WREG32(mmSCRATCH_ADDR, 0);
>   
>   	/* ring 0 - compute and gfx */
> -	/* Set ring buffer size */
>   	ring = &adev->gfx.gfx_ring[0];
> +	atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
> +	atomic64_set((atomic64_t *)ring->rptr_cpu_addr, 0);

One day we need to fix this whole atomic64 situation.

Regards,

Tvrtko

> +
> +	if (amdgpu_in_reset(adev))
> +		amdgpu_ring_clear_ring(ring);
> +
> +	/* Set ring buffer size */
>   	rb_bufsz = order_base_2(ring->ring_size / 8);
>   	tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
>   #ifdef __BIG_ENDIAN
> @@ -2559,6 +2565,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
>   	WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
>   	ring->wptr = 0;
>   	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
> +	WREG32(mmCP_RB0_RPTR, lower_32_bits(ring->wptr));
>   
>   	/* set the wb address whether it's enabled or not */
>   	rptr_addr = ring->rptr_gpu_addr;