RE: [PATCH 2/5] drm/amd/ras: update flip bit setting for uniras

AMD General

The patch is

Reviewed-by: Hawking Zhang <[email protected]>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <[email protected]> On Behalf Of Tao Zhou
Sent: Wednesday, July 15, 2026 3:48 PM
To: [email protected]
Cc: Zhou1, Tao <[email protected]>
Subject: [PATCH 2/5] drm/amd/ras: update flip bit setting for uniras

The flip bit setting is different if umc number is half of original configuration.

Signed-off-by: Tao Zhou <[email protected]>
---
 .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c  |   1 +
 drivers/gpu/drm/amd/ras/rascore/ras.h         |   1 +
 drivers/gpu/drm/amd/ras/rascore/ras_umc.c     |   1 +
 drivers/gpu/drm/amd/ras/rascore/ras_umc.h     |   1 +
 .../gpu/drm/amd/ras/rascore/ras_umc_v12_0.c   | 114 ++++++++++++------
 5 files changed, 84 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
index 60412da69b2b..c55288c2df9a 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
@@ -284,6 +284,7 @@ static int amdgpu_ras_mgr_init_umc_config(struct amdgpu_device *adev,
        struct ras_umc_config *umc_cfg = &config->umc_cfg;

        umc_cfg->umc_vram_type = adev->gmc.vram_type;
+       umc_cfg->num_umc = adev->gmc.num_umc;

        return 0;
 }
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
index 5869bad978b0..5719bc1b6167 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
@@ -277,6 +277,7 @@ struct ras_psp_config {

 struct ras_umc_config {
        uint32_t umc_vram_type;
+       uint32_t num_umc;
 };

 struct ras_eeprom_config {
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
index e366fb97293e..dd7a37163110 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
@@ -691,6 +691,7 @@ int ras_umc_hw_init(struct ras_core_context *ras_core)
        ras_umc->umc_err_data.umc_nps_mode = nps;

        ras_umc->umc_vram_type = ras_core->config->umc_cfg.umc_vram_type;
+       ras_umc->num_umc = ras_core->config->umc_cfg.num_umc;
        if (!ras_umc->umc_vram_type) {
                RAS_DEV_ERR(ras_core->dev, "Invalid UMC VRAM Type: %u!\n",
                        ras_umc->umc_vram_type);
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h
index ee7100f25f51..71b6703193f5 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h
@@ -137,6 +137,7 @@ struct ras_umc_err_data {  struct ras_umc {
        u32 umc_ip_version;
        u32 umc_vram_type;
+       u32 num_umc;
        const struct ras_umc_ip_func *ip_func;
        struct radix_tree_root root;
        struct mutex  tree_lock;
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
index b809a2f21d73..809cbd846883 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
@@ -64,51 +64,97 @@ static void __get_nps_pa_flip_bits(struct ras_core_context *ras_core,
                        struct umc_flip_bits *flip_bits)
 {
        uint32_t vram_type = ras_core->ras_umc.umc_vram_type;
-
-       /* default setting */
-       flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT;
-       flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT;
-       flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT;
-       flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT;
-       flip_bits->flip_row_bit = 13;
-       flip_bits->bit_num = 4;
-       flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT;
-
-       if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) {
+       uint32_t num_umc = ras_core->ras_umc.num_umc;
+
+       if (num_umc == 16) {
+               /* default setting */
+               flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT;
+               flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT;
+               flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT;
+               flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT;
+               flip_bits->flip_row_bit = 13;
+               flip_bits->bit_num = 4;
+               flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT;
+
+               if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) {
+                       flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;
+                       flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;
+                       flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;
+                       flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;
+               } else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4) {
+                       flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
+                       flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
+                       flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
+                       flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
+               }
+
+               switch (vram_type) {
+               case UMC_VRAM_TYPE_HBM:
+                       /* other nps modes are taken as nps1 */
+                       if (nps == UMC_MEMORY_PARTITION_MODE_NPS2)
+                               flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
+                       else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4)
+                               flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
+
+                       break;
+               case UMC_VRAM_TYPE_HBM3E:
+                       flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
+                       flip_bits->flip_row_bit = 12;
+
+                       if (nps == UMC_MEMORY_PARTITION_MODE_NPS2)
+                               flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
+                       else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4)
+                               flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;
+
+                       break;
+               default:
+                       RAS_DEV_WARN(ras_core->dev,
+                               "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n");
+                       break;
+               }
+       } else if (num_umc == 8) {
+               /* default setting */
                flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;
                flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;
                flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;
+               flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
+               flip_bits->flip_row_bit = 12;
+               flip_bits->bit_num = 4;
                flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;
-       } else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4) {
-               flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
-               flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
-               flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
-               flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
-       }

-       switch (vram_type) {
-       case UMC_VRAM_TYPE_HBM:
-               /* other nps modes are taken as nps1 */
-               if (nps == UMC_MEMORY_PARTITION_MODE_NPS2)
+               if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) {
+                       flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
+                       flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
+                       flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
+                       flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
+               }
+
+               switch (vram_type) {
+               case UMC_VRAM_TYPE_HBM:
                        flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
-               else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4)
-                       flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;

-               break;
-       case UMC_VRAM_TYPE_HBM3E:
-               flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
-               flip_bits->flip_row_bit = 12;
+                       /* other nps modes are taken as nps1 */
+                       if (nps == AMDGPU_NPS2_PARTITION_MODE)
+                               flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;

-               if (nps == UMC_MEMORY_PARTITION_MODE_NPS2)
+                       break;
+               case UMC_VRAM_TYPE_HBM3E:
                        flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
-               else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4)
-                       flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;
+                       flip_bits->flip_row_bit = 12;
+
+                       if (nps == UMC_MEMORY_PARTITION_MODE_NPS2)
+                               flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;

-               break;
-       default:
+                       break;
+               default:
+                       RAS_DEV_WARN(ras_core->dev,
+                               "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n");
+                               break;
+               }
+       } else {
                RAS_DEV_WARN(ras_core->dev,
-                       "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n");
-               break;
+                       "Unsupported UMC number(%d), failed to set RAS flip bits.\n",
+                       num_umc);
        }
 }

--
2.34.1