RE: [PATCH V4] drm/amdgpu/ras: Add debug mask to disable CE logs for uniras

"Zhou1, Tao" <[email protected]>
Newsgroups org.freedesktop.lists.amd-gfx
Message-ID <BL1PR12MB51277A020AC5942546487495B0C62@BL1PR12MB5127.namprd12.prod.outlook.com>
AMD General

Reviewed-by: Tao Zhou <[email protected]>

> -----Original Message-----
> From: Sun, Ce(Overlord) <[email protected]>
> Sent: Thursday, July 16, 2026 5:27 PM
> To: [email protected]
> Cc: Zhang, Hawking <[email protected]>; Chai, Thomas
> <[email protected]>; Zhou1, Tao <[email protected]>; Yang, Stanley
> <[email protected]>; Sun, Ce(Overlord) <[email protected]>
> Subject: [PATCH V4] drm/amdgpu/ras: Add debug mask to disable CE logs for uniras
>
> Add debug mask to disable kernel logs of RAS correctable errors, including both ACA
> and CE error counter kernel messages.
>
> Signed-off-by: Ce Sun <[email protected]>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h             |  1 +
>  .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c    |  1 +
>  drivers/gpu/drm/amd/ras/rascore/ras.h           |  2 ++
>  drivers/gpu/drm/amd/ras/rascore/ras_aca.c       | 17 ++++++++++-------
>  drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c  |  2 +-
>  drivers/gpu/drm/amd/ras/rascore/ras_core.c      |  9 +++++++++
>  6 files changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index a3dafdca7eb3..bc6b7da3914f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -226,6 +226,7 @@ extern int amdgpu_use_xgmi_p2p;  extern bool pcie_p2p;
> extern int amdgpu_mtype_local;  extern int amdgpu_enforce_isolation;
> +extern uint amdgpu_debug_mask;
>  #ifdef CONFIG_HSA_AMD
>  extern int sched_policy;
>  extern bool debug_evictions;
> diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
> b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
> index ea95e0f93d1c..0db755ba7037 100644
> --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
> +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
> @@ -309,6 +309,7 @@ static struct ras_core_context
> *amdgpu_ras_mgr_create_ras_core(struct amdgpu_dev
>               amdgpu_ras_mgr_eeprom_is_supported(adev);
>       init_config.poison_supported =
>               amdgpu_ras_is_poison_mode_supported(adev);
> +     init_config.ras_debug_mask = amdgpu_debug_mask;
>
>       amdgpu_ras_mgr_init_aca_config(adev, &init_config);
>       amdgpu_ras_mgr_init_eeprom_config(adev, &init_config); diff --git
> a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
> index 878dfdfcb18a..88b0bac158af 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
> @@ -301,6 +301,7 @@ struct ras_core_config {
>
>       bool poison_supported;
>       bool ras_eeprom_supported;
> +     uint ras_debug_mask;
>       const struct ras_sys_func *sys_fn;
>
>       struct ras_aca_config aca_cfg;
> @@ -403,4 +404,5 @@ int ras_core_convert_soc_pa_to_cur_nps_pages(struct
> ras_core_context *ras_core,  int ras_core_check_address_sanity(struct
> ras_core_context *ras_core, uint64_t addr);
>
>  int ras_core_set_debug_mode(struct ras_core_context *ras_core, bool enable);
> +bool ras_core_is_ce_log_disabled(struct ras_core_context *ras_core);
>  #endif
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c
> b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c
> index 67a35409ff0e..a1fb9a5f72cf 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c
> @@ -83,22 +83,20 @@ static void aca_report_ecc_info(struct ras_core_context
> *ras_core,
>                       seq_no, skt, aid, ecc_count.total_ue_count, blk_name(blk));
>       }
>
> -     if (ecc_count.new_de_count) {
> +     if (ecc_count.new_de_count && blk == RAS_BLOCK_ID__UMC) {
>               RAS_DEV_INFO(ras_core->dev,
> -             "{%llu} socket: %d, die: %d, %u new %s detected in %s block\n",
> +             "{%llu} socket: %d, die: %d, %u new deferred hardware errors
> detected
> +in %s block\n",
>                       seq_no, skt, aid, ecc_count.new_de_count,
> -                     (blk == RAS_BLOCK_ID__UMC) ?
> -                             "deferred hardware errors" : "poison consumption",
>                       blk_name(blk));
>               RAS_DEV_INFO(ras_core->dev,
> -             "{%llu} socket: %d, die: %d, %u %s detected in total in %s block\n",
> +             "{%llu} socket: %d, die: %d, %u deferred hardware errors detected in
> +total in %s block\n",
>                       seq_no, skt, aid, ecc_count.total_de_count,
> -                     (blk == RAS_BLOCK_ID__UMC) ?
> -                             "deferred hardware errors" : "poison consumption",
>                       blk_name(blk));
>       }
>
>       if (ecc_count.new_ce_count) {
> +             if (ras_core_is_ce_log_disabled(ras_core))
> +                     return;
>               RAS_DEV_INFO(ras_core->dev,
>               "{%llu} socket: %d, die: %d, %u new correctable hardware errors
> detected in %s block\n",
>                       seq_no, skt, aid, ecc_count.new_ce_count, blk_name(blk));
> @@ -114,6 +112,11 @@ static void aca_bank_log(struct ras_core_context
> *ras_core,  {
>       int i;
>
> +     if(ras_core_is_ce_log_disabled(ras_core) &&
> +        bank->ecc_type == RAS_ERR_TYPE__CE &&
> +        !bank_ecc->de_count)
> +             return;
> +
>       RAS_DEV_INFO(ras_core->dev,
>               "{%llu}" RAS_HW_ERR "Accelerator Check Architecture events
> logged\n",
>               bank->seq_no);
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c
> b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c
> index 840610538c1f..288fad0862a2 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c
> @@ -265,7 +265,7 @@ static int aca_parse_bank_default(struct ras_core_context
> *ras_core,
>       ecc->bank_info.addr = bank->regs[ACA_REG_IDX__ADDR];
>
>       if (aca_check_bank_is_de(ras_core, status)) {
> -             ecc->de_count = 0;
> +             ecc->de_count = 1;
>       } else {
>               if (bank->ecc_type == RAS_ERR_TYPE__UE)
>                       ecc->ue_count = 1;
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> index 08e17a83ad5b..c90db914aa5f 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> @@ -28,6 +28,10 @@
>
>  #define IS_LEAP_YEAR(x) ((x % 4 == 0 && x % 100 != 0) || x % 400 == 0)
>
> +enum RAS_DEBUG_MASK {
> +     RAS_DEBUG_DISABLE_RAS_CE_LOG = 9,
> +};
> +
>  static const char * const ras_block_name[] = {
>       "umc",
>       "sdma",
> @@ -545,6 +549,11 @@ bool ras_core_is_enabled(struct ras_core_context
> *ras_core)
>       return ras_core->ras_core_enabled;
>  }
>
> +bool ras_core_is_ce_log_disabled(struct ras_core_context *ras_core) {
> +     return !!(ras_core->config->ras_debug_mask &
> +BIT(RAS_DEBUG_DISABLE_RAS_CE_LOG));
> +}
> +
>  uint64_t ras_core_get_utc_second_timestamp(struct ras_core_context *ras_core)  {
>       if (!ras_core)
> --
> 2.34.1
lmpx.com only provides a reader for public news (NNTP) servers. It is not affiliated with the servers or forums shown here and is not responsible for the content of articles, which is written by their respective authors.