Re: [PATCH] drm/amd/ras: wait for PMFW MCA polling in UniRAS recovery
"Liu, Xiang(Dean)" <[email protected]> Fri, 31 Jul 2026 15:03:13 +0000
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--_000_CY5PR12MB6345E08E9BA84E8C62475A4DFAC82CY5PR12MB6345namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable AMD General Sure, will improve it, thanks. Best Regards, Liu, Xiang ________________________________ From: Chai, Thomas <[email protected]> Sent: Friday, July 31, 2026 3:12 PM To: Liu, Xiang(Dean) <[email protected]>; [email protected] <am= [email protected]> Cc: Zhang, Hawking <[email protected]>; Zhou1, Tao <[email protected]>;= Yang, Stanley <[email protected]> Subject: RE: [PATCH] drm/amd/ras: wait for PMFW MCA polling in UniRAS recov= ery AMD General If this delay is only intended for fatal recovery, should it also be condit= ioned on gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET? An unconditional msleep here would unnecessarily impact other reset paths (= e.g., mode2 reset). Best Regards, Thomas -----Original Message----- From: Liu, Xiang(Dean) <[email protected]> Sent: Friday, July 31, 2026 1:44 PM To: [email protected] Cc: Zhang, Hawking <[email protected]>; Zhou1, Tao <[email protected]>;= Yang, Stanley <[email protected]>; Chai, Thomas <[email protected]>; = Liu, Xiang(Dean) <[email protected]> Subject: [PATCH] drm/amd/ras: wait for PMFW MCA polling in UniRAS recovery UniRAS fatal recovery reads MCA-derived ECC data through PMFW, but direct q= uery mode bypasses the existing firmware-query delay. The recovery worker c= an therefore query before PMFW has finished polling the MCA banks, causing = the first fatal injection to miss its UE count or time out. Apply the same 500 ms settle delay whenever UniRAS is enabled before harves= ting ECC data. Signed-off-by: Xiang Liu <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ras.c index d247d0ad063f..ad9a9545b1d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2755,7 +2755,10 @@ static void amdgpu_ras_do_recovery(struct work_struc= t *work) device_list_handle =3D &device_list; } - if (amdgpu_ras_get_error_query_mode(adev, &error_query_mode= )) { + if (amdgpu_uniras_enabled(adev)) { + /* wait 500ms to ensure pmfw polling mca bank info = done */ + msleep(500); + } else if (amdgpu_ras_get_error_query_mode(adev, &error_que= ry_mode)) +{ if (error_query_mode =3D=3D AMDGPU_RAS_FIRMWARE_ERR= OR_QUERY) { /* wait 500ms to ensure pmfw polling mca ba= nk info done */ msleep(500); -- 2.34.1 --_000_CY5PR12MB6345E08E9BA84E8C62475A4DFAC82CY5PR12MB6345namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable <html> <head> <meta http-equiv=3D"Content-Type" content=3D"text/html; charset=3Dus-ascii"= > <style type=3D"text/css" style=3D"display:none;"> P {margin-top:0;margin-bo= ttom:0;} </style> </head> <body dir=3D"ltr"> <div> <div style=3D"font-family: Calibri; text-align: left; color: rgb(0, 0, 255)= ; margin-left: 5pt; font-size: 10pt;"> AMD General</div> <br> </div> <div class=3D"elementToProof" style=3D"text-align: left; text-indent: 0px; = background-color: white; margin: 0px; font-family: Calibri, Helvetica, sans= -serif; font-size: 11pt; color: black;"> Sure, will improve it, thanks.</div> <p class=3D"elementToProof" style=3D"direction: ltr; text-align: left; text= -indent: 0px; background-color: white; margin-top: 0px; margin-bottom: 0px;= "> <span style=3D"font-family: Calibri, Helvetica, sans-serif; font-size: 11pt= ; color: black;">Best Regards,</span></p> <p class=3D"elementToProof" style=3D"direction: ltr; text-align: left; text= -indent: 0px; background-color: white; margin-top: 0px; margin-bottom: 0px;= "> <span style=3D"font-family: Calibri, Helvetica, sans-serif; font-size: 11pt= ; color: rgb(36, 36, 36);">Liu, Xiang</span></p> <div style=3D"font-family: Calibri, Helvetica, sans-serif; font-size: 11pt;= color: rgb(0, 0, 0);"> <br> </div> <div id=3D"appendonsend"></div> <hr style=3D"display:inline-block;width:98%" tabindex=3D"-1"> <div id=3D"divRplyFwdMsg" dir=3D"ltr"><font face=3D"Calibri, sans-serif" st= yle=3D"font-size:11pt" color=3D"#000000"><b>From:</b> Chai, Thomas <YiPe= [email protected]><br> <b>Sent:</b> Friday, July 31, 2026 3:12 PM<br> <b>To:</b> Liu, Xiang(Dean) <[email protected]>; [email protected]= sktop.org <[email protected]><br> <b>Cc:</b> Zhang, Hawking <[email protected]>; Zhou1, Tao <Tao= [email protected]>; Yang, Stanley <[email protected]><br> <b>Subject:</b> RE: [PATCH] drm/amd/ras: wait for PMFW MCA polling in UniRA= S recovery</font> <div> </div> </div> <div class=3D"BodyFragment"><font face=3D"Times New Roman" size=3D"3"><span= style=3D"font-size:12pt;"><a name=3D"BM_BEGIN"></a> <div><font size=3D"2"><span style=3D"font-size:11pt;">AMD General<br> <br> If this delay is only intended for fatal recovery, should it also be condit= ioned on gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET?<br> An unconditional msleep here would unnecessarily impact other reset paths (= e.g., mode2 reset).<br> <br> Best Regards,<br> Thomas<br> -----Original Message-----<br> From: Liu, Xiang(Dean) <[email protected]><br> Sent: Friday, July 31, 2026 1:44 PM<br> To: [email protected]<br> Cc: Zhang, Hawking <[email protected]>; Zhou1, Tao <Tao.Zhou1@= amd.com>; Yang, Stanley <[email protected]>; Chai, Thomas <Y= [email protected]>; Liu, Xiang(Dean) <[email protected]><br> Subject: [PATCH] drm/amd/ras: wait for PMFW MCA polling in UniRAS recovery<= br> <br> UniRAS fatal recovery reads MCA-derived ECC data through PMFW, but direct q= uery mode bypasses the existing firmware-query delay. The recovery worker c= an therefore query before PMFW has finished polling the MCA banks, causing = the first fatal injection to miss its UE count or time out.<br> <br> Apply the same 500 ms settle delay whenever UniRAS is enabled before harves= ting ECC data.<br> <br> Signed-off-by: Xiang Liu <[email protected]><br> ---<br> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 ++++-<br> 1 file changed, 4 insertions(+), 1 deletion(-)<br> <br> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ras.c<br> index d247d0ad063f..ad9a9545b1d6 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br> @@ -2755,7 +2755,10 @@ static void amdgpu_ras_do_recovery(struct work_struc= t *work)<br> &nb= sp; device_list= _handle =3D &device_list;<br> &nb= sp; }<br> <br> - &n= bsp; if (amdgpu_ras_get_error_query_mode(adev, &error_query_mode)= ) {<br> + &n= bsp; if (amdgpu_uniras_enabled(adev)) {<br> + &n= bsp; /* wait 500ms to= ensure pmfw polling mca bank info done */<br> + &n= bsp; msleep(500);<br> + &n= bsp; } else if (amdgpu_ras_get_error_query_mode(adev, &error_quer= y_mode))<br> +{<br> &nb= sp; if (error_q= uery_mode =3D=3D AMDGPU_RAS_FIRMWARE_ERROR_QUERY) {<br> &nb= sp; = /* wait 500ms to ensure pmfw polling m= ca bank info done */<br> &nb= sp; = msleep(500);<br> --<br> 2.34.1<br> <br> </span></font></div> </span></font></div> </body> </html> --_000_CY5PR12MB6345E08E9BA84E8C62475A4DFAC82CY5PR12MB6345namp_--