RE: [PATCH v2 2/2] drm/amdkfd: enable rs64mem for kfd queue

AMD General

Ping..

Regards,
      Prike

> -----Original Message-----
> From: Liang, Prike <[email protected]>
> Sent: Thursday, July 30, 2026 10:09 AM
> To: [email protected]
> Cc: Deucher, Alexander <[email protected]>; Koenig, Christian
> <[email protected]>; Chen, Michael <[email protected]>; Liu,
> Shaoyun <[email protected]>; Liang, Prike <[email protected]>
> Subject: [PATCH v2 2/2] drm/amdkfd: enable rs64mem for kfd queue
>
> Enabled RS64mem for KFD queues by integrating process and gang context in=
dex
> allocation in the per KFD device process and queue creation.
>
> Signed-off-by: Prike Liang <[email protected]>
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  |  3 +++
>  drivers/gpu/drm/amd/amdkfd/kfd_priv.h                  |  3 +++
>  drivers/gpu/drm/amd/amdkfd/kfd_process.c               |  5 ++++-
>  drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 10 ++++++++++
>  4 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index 51ee9c39104b..ea9d87450eae 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -226,8 +226,10 @@ static int add_queue_mes(struct device_queue_manager
> *dqm, struct queue *q,
>       /* MES unit for quantum is 100ns */
>       queue_input.process_quantum =3D KFD_MES_PROCESS_QUANTUM;  /*
> Equivalent to 10ms. */
>       queue_input.process_context_addr =3D pdd->proc_ctx_gpu_addr;
> +     queue_input.process_context_array_index =3D pdd->proc_ctx_array_ind=
ex;
>       queue_input.gang_quantum =3D KFD_MES_GANG_QUANTUM; /* Equivalent
> to 1ms */
>       queue_input.gang_context_addr =3D q->gang_ctx_gpu_addr;
> +     queue_input.gang_context_array_index =3D q->gang_ctx_array_index;
>       queue_input.inprocess_gang_priority =3D q->properties.priority;
>       queue_input.gang_global_priority_level =3D
>
>       AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
> @@ -303,6 +305,7 @@ static int remove_queue_mes_on_reset_option(struct
> device_queue_manager *dqm, st
>       queue_input.queue_type =3D convert_to_amdgpu_ring_type(q-
> >properties.type);
>       queue_input.remove_queue_after_reset =3D flush_mes_queue;
>       queue_input.xcc_id =3D ffs(dqm->dev->xcc_mask) - 1;
> +     queue_input.gang_context_array_index =3D q->gang_ctx_array_index;
>
>       amdgpu_mes_lock(&adev->mes);
>       r =3D adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); d=
iff -
> -git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> index 88191a4c1657..3b89bcc625b3 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> @@ -635,6 +635,7 @@ struct queue {
>       void *gang_ctx_bo;
>       uint64_t gang_ctx_gpu_addr;
>       void *gang_ctx_cpu_ptr;
> +     uint32_t gang_ctx_array_index;
>
>       struct amdgpu_bo *wptr_bo_gart;
>  };
> @@ -871,6 +872,8 @@ struct kfd_process_device {
>       uint64_t proc_ctx_gpu_addr;
>       void *proc_ctx_cpu_ptr;
>
> +     uint32_t proc_ctx_array_index;
> +
>       /* Tracks queue reset status */
>       bool has_reset_queue;
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> index eb508fe3ded7..0a7c1900da95 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> @@ -1215,9 +1215,12 @@ static void kfd_process_destroy_pdds(struct
> kfd_process *p)
>               kfd_free_process_doorbells(pdd->dev->kfd, pdd);
>
>               if (pdd->dev->kfd->shared_resources.enable_mes &&
> -                     pdd->proc_ctx_cpu_ptr)
> +                     pdd->proc_ctx_cpu_ptr) {
> +                     amdgpu_mes_free_proc_ctx_index(&pdd->dev->adev->mes=
,
> +                                                    pdd->proc_ctx_array_=
index);
>                       amdgpu_amdkfd_free_kernel_mem(pdd->dev->adev,
>                                                  &pdd->proc_ctx_bo);
> +             }
>               /*
>                * before destroying pdd, make sure to report availability
>                * for auto suspend
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> index 8054e4fe0381..72913b5c8338 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> @@ -210,6 +210,7 @@ static void pqm_clean_queue_resource(struct
> process_queue_manager *pqm,
>       }
>
>       if (dev->kfd->shared_resources.enable_mes) {
> +             amdgpu_mes_free_gang_ctx_index(&dev->adev->mes,
> +pqn->q->gang_ctx_array_index);
>               amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn->q-
> >gang_ctx_bo);
>               amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)&pqn->q-
> >wptr_bo_gart);
>       }
> @@ -282,6 +283,9 @@ static int init_user_queue(struct process_queue_manag=
er
> *pqm,
>                       goto cleanup;
>               }
>               memset((*q)->gang_ctx_cpu_ptr, 0,
> AMDGPU_MES_GANG_CTX_SIZE);
> +             /* Bind one MES gang context slot per queue (gang). */
> +             amdgpu_mes_alloc_gang_ctx_index(&dev->adev->mes,
> +                                             &(*q)->gang_ctx_array_index=
);
>
>               /* Starting with GFX11, wptr BOs must be mapped to GART for=
 MES
> to determine work
>                * on unmapped queues for usermode queue oversubscription (=
no
> aggregated doorbell) @@ -304,6 +308,7 @@ static int init_user_queue(struc=
t
> process_queue_manager *pqm,
>       return 0;
>
>  free_gang_ctx_bo:
> +     amdgpu_mes_free_gang_ctx_index(&dev->adev->mes,
> +(*q)->gang_ctx_array_index);
>       amdgpu_amdkfd_free_kernel_mem(dev->adev, &(*q)->gang_ctx_bo);
>  cleanup:
>       uninit_queue(*q);
> @@ -386,6 +391,11 @@ int pqm_create_queue(struct process_queue_manager
> *pqm,
>                       goto err_allocate_pqn;
>               }
>               memset(pdd->proc_ctx_cpu_ptr, 0,
> AMDGPU_MES_PROC_CTX_SIZE);
> +             /* Bind one MES process context slot to the whole process
> +              * (per device); every queue of this process reuses it.
> +              */
> +             amdgpu_mes_alloc_proc_ctx_index(&dev->adev->mes,
> +                                             &pdd->proc_ctx_array_index)=
;
>       }
>
>       pqn =3D kzalloc_obj(*pqn);
> --
> 2.34.1