RE: [PATCH v2 2/2] drm/amdkfd: enable rs64mem for kfd queue
"Liang, Prike" <[email protected]> Tue, 4 Aug 2026 02:41:47 +0000
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AMD General
Regards,
Prike
From: amd-gfx <[email protected]> On Behalf Of Liang, P=
rike
Sent: Tuesday, August 4, 2026 9:57 AM
To: Chen, Michael <[email protected]>; [email protected]
Cc: Deucher, Alexander <[email protected]>; Koenig, Christian <Chri=
[email protected]>; Liu, Shaoyun <[email protected]>
Subject: RE: [PATCH v2 2/2] drm/amdkfd: enable rs64mem for kfd queue
AMD General
Regards,
Prike
From: Chen, Michael <[email protected]<mailto:[email protected]>>
Sent: Tuesday, August 4, 2026 4:31 AM
To: Liang, Prike <[email protected]<mailto:[email protected]>>; amd-gfx=
@lists.freedesktop.org<mailto:[email protected]>
Cc: Deucher, Alexander <[email protected]<mailto:Alexander.Deucher@=
amd.com>>; Koenig, Christian <[email protected]<mailto:Christian.Koe=
[email protected]>>; Liu, Shaoyun <[email protected]<mailto:[email protected]=
>>
Subject: Re: [PATCH v2 2/2] drm/amdkfd: enable rs64mem for kfd queue
AMD General
________________________________
From: Liang, Prike <[email protected]<mailto:[email protected]>>
Sent: Wednesday, July 29, 2026 10:09 PM
To: [email protected]<mailto:[email protected]> <am=
[email protected]<mailto:[email protected]>>
Cc: Deucher, Alexander <[email protected]<mailto:Alexander.Deucher@=
amd.com>>; Koenig, Christian <[email protected]<mailto:Christian.Koe=
[email protected]>>; Chen, Michael <[email protected]<mailto:Michael.Chen@amd.=
com>>; Liu, Shaoyun <[email protected]<mailto:[email protected]>>; Lian=
g, Prike <[email protected]<mailto:[email protected]>>
Subject: [PATCH v2 2/2] drm/amdkfd: enable rs64mem for kfd queue
Enabled RS64mem for KFD queues by integrating
process and gang context index allocation in
the per KFD device process and queue creation.
Signed-off-by: Prike Liang <[email protected]<mailto:[email protected]>=
>
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +++
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 5 ++++-
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 10 ++++++++++
4 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/driver=
s/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 51ee9c39104b..ea9d87450eae 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -226,8 +226,10 @@ static int add_queue_mes(struct device_queue_manager *=
dqm, struct queue *q,
/* MES unit for quantum is 100ns */
queue_input.process_quantum =3D KFD_MES_PROCESS_QUANTUM; /* Equiv=
alent to 10ms. */
queue_input.process_context_addr =3D pdd->proc_ctx_gpu_addr;
+ queue_input.process_context_array_index =3D pdd->proc_ctx_array_ind=
ex;
queue_input.gang_quantum =3D KFD_MES_GANG_QUANTUM; /* Equivalent t=
o 1ms */
queue_input.gang_context_addr =3D q->gang_ctx_gpu_addr;
+ queue_input.gang_context_array_index =3D q->gang_ctx_array_index;
queue_input.inprocess_gang_priority =3D q->properties.priority;
queue_input.gang_global_priority_level =3D
AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
@@ -303,6 +305,7 @@ static int remove_queue_mes_on_reset_option(struct devi=
ce_queue_manager *dqm, st
queue_input.queue_type =3D convert_to_amdgpu_ring_type(q->properti=
es.type);
queue_input.remove_queue_after_reset =3D flush_mes_queue;
queue_input.xcc_id =3D ffs(dqm->dev->xcc_mask) - 1;
+ queue_input.gang_context_array_index =3D q->gang_ctx_array_index;
amdgpu_mes_lock(&adev->mes);
r =3D adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/am=
dkfd/kfd_priv.h
index 88191a4c1657..3b89bcc625b3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -635,6 +635,7 @@ struct queue {
void *gang_ctx_bo;
uint64_t gang_ctx_gpu_addr;
void *gang_ctx_cpu_ptr;
+ uint32_t gang_ctx_array_index;
struct amdgpu_bo *wptr_bo_gart;
};
@@ -871,6 +872,8 @@ struct kfd_process_device {
uint64_t proc_ctx_gpu_addr;
void *proc_ctx_cpu_ptr;
+ uint32_t proc_ctx_array_index;
+
/* Tracks queue reset status */
bool has_reset_queue;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd=
/amdkfd/kfd_process.c
index eb508fe3ded7..0a7c1900da95 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -1215,9 +1215,12 @@ static void kfd_process_destroy_pdds(struct kfd_proc=
ess *p)
kfd_free_process_doorbells(pdd->dev->kfd, pdd);
if (pdd->dev->kfd->shared_resources.enable_mes &&
- pdd->proc_ctx_cpu_ptr)
+ pdd->proc_ctx_cpu_ptr) {
+ amdgpu_mes_free_proc_ctx_index(&pdd->dev->adev->mes=
,
+ pdd->proc_ctx_array_=
index);
amdgpu_amdkfd_free_kernel_mem(pdd->dev->adev,
&pdd->proc_ctx_bo);
+ }
/*
* before destroying pdd, make sure to report availability
* for auto suspend
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drive=
rs/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index 8054e4fe0381..72913b5c8338 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -210,6 +210,7 @@ static void pqm_clean_queue_resource(struct process_que=
ue_manager *pqm,
}
if (dev->kfd->shared_resources.enable_mes) {
+ amdgpu_mes_free_gang_ctx_index(&dev->adev->mes, pqn->q->gan=
g_ctx_array_index);
amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn->q->gang_ctx=
_bo);
amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)&pqn->q-=
>wptr_bo_gart);
}
@@ -282,6 +283,9 @@ static int init_user_queue(struct process_queue_manager=
*pqm,
goto cleanup;
}
memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE=
);
+ /* Bind one MES gang context slot per queue (gang). */
+ amdgpu_mes_alloc_gang_ctx_index(&dev->adev->mes,
+ &(*q)->gang_ctx_array_index=
);
1. Should check "mes->use_rs64mem" as you do in patch #1?
It doesn't have to check here, since the rs64mem support will be checked in=
the amdgpu_mes_alloc_gang_ctx_index() as well.
>> Think more about it, we may still need to check the rs64mem flag at the =
invocation place to make the case which disables the rs64mem work properly.
1. Check return error code (in oversubscription case, it may run out of =
index)
Yeah, we add the error handler.
/* Starting with GFX11, wptr BOs must be mapped to GART fo=
r MES to determine work
* on unmapped queues for usermode queue oversubscription =
(no aggregated doorbell)
@@ -304,6 +308,7 @@ static int init_user_queue(struct process_queue_manager=
*pqm,
return 0;
free_gang_ctx_bo:
+ amdgpu_mes_free_gang_ctx_index(&dev->adev->mes, (*q)->gang_ctx_arra=
y_index);
amdgpu_amdkfd_free_kernel_mem(dev->adev, &(*q)->gang_ctx_bo);
cleanup:
uninit_queue(*q);
@@ -386,6 +391,11 @@ int pqm_create_queue(struct process_queue_manager *pqm=
,
goto err_allocate_pqn;
}
memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE)=
;
+ /* Bind one MES process context slot to the whole process
+ * (per device); every queue of this process reuses it.
+ */
+ amdgpu_mes_alloc_proc_ctx_index(&dev->adev->mes,
+ &pdd->proc_ctx_array_index)=
;
Same comment as above.
}
pqn =3D kzalloc_obj(*pqn);
--
2.34.1
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AMD General<br>
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font-family:"Calibri",sans-serif"> amd-gfx <amd-gfx-bounces@li=
sts.freedesktop.org>
<b>On Behalf Of </b>Liang, Prike<br>
<b>Sent:</b> Tuesday, August 4, 2026 9:57 AM<br>
<b>To:</b> Chen, Michael <[email protected]>; [email protected]=
sktop.org<br>
<b>Cc:</b> Deucher, Alexander <[email protected]>; Koenig, Ch=
ristian <[email protected]>; Liu, Shaoyun <Shaoyun.Liu@amd.=
com><br>
<b>Subject:</b> RE: [PATCH v2 2/2] drm/amdkfd: enable rs64mem for kfd queue=
<o:p></o:p></span></p>
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<p style=3D"margin:5.0pt"><span style=3D"font-size:10.0pt;font-family:"=
;Calibri",sans-serif;color:blue">AMD General<o:p></o:p></span></p>
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rdcontextual">Regards,<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt;mso-ligatures:standa=
rdcontextual"> Prike<o:p></o:p></span></p>
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;Calibri",sans-serif">From:</span></b><span style=3D"font-size:11.0pt;=
font-family:"Calibri",sans-serif"> Chen, Michael <<a href=3D"m=
ailto:[email protected]">[email protected]</a>>
<br>
<b>Sent:</b> Tuesday, August 4, 2026 4:31 AM<br>
<b>To:</b> Liang, Prike <<a href=3D"mailto:[email protected]">Prike.Li=
[email protected]</a>>;
<a href=3D"mailto:[email protected]">[email protected].=
org</a><br>
<b>Cc:</b> Deucher, Alexander <<a href=3D"mailto:[email protected]=
om">[email protected]</a>>; Koenig, Christian <<a href=3D"mai=
lto:[email protected]">[email protected]</a>>; Liu, Shaoyu=
n <<a href=3D"mailto:[email protected]">[email protected]</a>><br=
>
<b>Subject:</b> Re: [PATCH v2 2/2] drm/amdkfd: enable rs64mem for kfd queue=
<o:p></o:p></span></p>
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<p class=3D"MsoNormal"><b><span style=3D"font-size:11.0pt;font-family:"=
;Calibri",sans-serif;color:black">From:</span></b><span style=3D"font-=
size:11.0pt;font-family:"Calibri",sans-serif;color:black"> Liang,=
Prike <<a href=3D"mailto:[email protected]">[email protected]</a>&g=
t;<br>
<b>Sent:</b> Wednesday, July 29, 2026 10:09 PM<br>
<b>To:</b> <a href=3D"mailto:[email protected]">[email protected]=
reedesktop.org</a> <<a href=3D"mailto:[email protected]">amd=
[email protected]</a>><br>
<b>Cc:</b> Deucher, Alexander <<a href=3D"mailto:[email protected]=
om">[email protected]</a>>; Koenig, Christian <<a href=3D"mai=
lto:[email protected]">[email protected]</a>>; Chen, Micha=
el <<a href=3D"mailto:[email protected]">[email protected]</a>>=
;
Liu, Shaoyun <<a href=3D"mailto:[email protected]">[email protected]=
m</a>>; Liang, Prike <<a href=3D"mailto:[email protected]">Prike.Li=
[email protected]</a>><br>
<b>Subject:</b> [PATCH v2 2/2] drm/amdkfd: enable rs64mem for kfd queue<o:p=
></o:p></span></p>
<p class=3D"MsoNormal"> <o:p></o:p></p>
</div>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt">Enabled RS64mem for=
KFD queues by integrating<br>
process and gang context index allocation in<br>
the per KFD device process and queue creation.<br>
<br>
Signed-off-by: Prike Liang <<a href=3D"mailto:[email protected]">Prike=
[email protected]</a>><br>
---<br>
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3=
+++<br>
drivers/gpu/drm/amd/amdkfd/kfd_priv.h &n=
bsp; |&nb=
sp; 3 +++<br>
drivers/gpu/drm/amd/amdkfd/kfd_process.c  =
; | 5 ++++-<br>
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 10 +++++++++=
+<br>
4 files changed, 20 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/driver=
s/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c<br>
index 51ee9c39104b..ea9d87450eae 100644<br>
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c<br>
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c<br>
@@ -226,8 +226,10 @@ static int add_queue_mes(struct device_queue_manager *=
dqm, struct queue *q,<br>
/* MES unit for quantum is=
100ns */<br>
queue_input.process_quantu=
m =3D KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */<br>
queue_input.process_contex=
t_addr =3D pdd->proc_ctx_gpu_addr;<br>
+ queue_input.process_context_array_ind=
ex =3D pdd->proc_ctx_array_index;<br>
queue_input.gang_quantum =
=3D KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */<br>
queue_input.gang_context_a=
ddr =3D q->gang_ctx_gpu_addr;<br>
+ queue_input.gang_context_array_index =
=3D q->gang_ctx_array_index;<br>
queue_input.inprocess_gang=
_priority =3D q->properties.priority;<br>
queue_input.gang_global_pr=
iority_level =3D<br>
&nb=
sp; =
&nb=
sp; AMDGPU_MES_PRIORITY_LEVEL_NORMAL;<br>
@@ -303,6 +305,7 @@ static int remove_queue_mes_on_reset_option(struct devi=
ce_queue_manager *dqm, st<br>
queue_input.queue_type =3D=
convert_to_amdgpu_ring_type(q->properties.type);<br>
queue_input.remove_queue_a=
fter_reset =3D flush_mes_queue;<br>
queue_input.xcc_id =3D ffs=
(dqm->dev->xcc_mask) - 1;<br>
+ queue_input.gang_context_array_index =
=3D q->gang_ctx_array_index;<br>
<br>
amdgpu_mes_lock(&adev-=
>mes);<br>
r =3D adev->mes.funcs-&=
gt;remove_hw_queue(&adev->mes, &queue_input);<br>
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/am=
dkfd/kfd_priv.h<br>
index 88191a4c1657..3b89bcc625b3 100644<br>
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h<br>
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h<br>
@@ -635,6 +635,7 @@ struct queue {<br>
void *gang_ctx_bo;<br>
uint64_t gang_ctx_gpu_addr=
;<br>
void *gang_ctx_cpu_ptr;<br=
>
+ uint32_t gang_ctx_array_index;<br>
<br>
struct amdgpu_bo *wptr_bo_=
gart;<br>
};<br>
@@ -871,6 +872,8 @@ struct kfd_process_device {<br>
uint64_t proc_ctx_gpu_addr=
;<br>
void *proc_ctx_cpu_ptr;<br=
>
<br>
+ uint32_t proc_ctx_array_index;<br>
+<br>
/* Tracks queue reset stat=
us */<br>
bool has_reset_queue;<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd=
/amdkfd/kfd_process.c<br>
index eb508fe3ded7..0a7c1900da95 100644<br>
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c<br>
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c<br>
@@ -1215,9 +1215,12 @@ static void kfd_process_destroy_pdds(struct kfd_proc=
ess *p)<br>
&nb=
sp; kfd_free_process_doorbells(pdd->dev->kfd, pdd);=
<br>
<br>
&nb=
sp; if (pdd->dev->kfd->shared_resources.enable_m=
es &&<br>
- &n=
bsp; pdd->proc_ctx=
_cpu_ptr)<br>
+ &n=
bsp; pdd->proc_ctx=
_cpu_ptr) {<br>
+ &n=
bsp; amdgpu_mes_free_=
proc_ctx_index(&pdd->dev->adev->mes,<br>
+ &n=
bsp;  =
; &n=
bsp;  =
; pdd->proc_ctx_array_index);<br>
&nb=
sp; amdgp=
u_amdkfd_free_kernel_mem(pdd->dev->adev,<br>
&nb=
sp; =
&nb=
sp; =
&pdd->proc_ctx_bo);<br>
+ &n=
bsp; }<br>
&nb=
sp; /*<br>
&nb=
sp; * before destroying pdd, make sure to report av=
ailability<br>
&nb=
sp; * for auto suspend<br>
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drive=
rs/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c<br>
index 8054e4fe0381..72913b5c8338 100644<br>
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c<br>
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c<br>
@@ -210,6 +210,7 @@ static void pqm_clean_queue_resource(struct process_que=
ue_manager *pqm,<br>
}<br>
<br>
if (dev->kfd->shared=
_resources.enable_mes) {<br>
+ &n=
bsp; amdgpu_mes_free_gang_ctx_index(&dev->adev->mes, pqn-&g=
t;q->gang_ctx_array_index);<br>
&nb=
sp; amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn-=
>q->gang_ctx_bo);<br>
&nb=
sp; amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)=
&pqn->q->wptr_bo_gart);<br>
}<br>
@@ -282,6 +283,9 @@ static int init_user_queue(struct process_queue_manager=
*pqm,<br>
&nb=
sp; goto =
cleanup;<br>
&nb=
sp; }<br>
&nb=
sp; memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_=
CTX_SIZE);<br>
+ &n=
bsp; /* Bind one MES gang context slot per queue (gang). */<br>
+ &n=
bsp; amdgpu_mes_alloc_gang_ctx_index(&dev->adev->mes,<br>
+ &n=
bsp;  =
; &n=
bsp; &(*q)->gang_ctx=
_array_index);<br>
<o:p></o:p></span></p>
<ol style=3D"margin-top:0in" start=3D"1" type=3D"1">
<li class=3D"MsoNormal" style=3D"color:black;mso-list:l2 level1 lfo3"><span=
style=3D"font-size:11.0pt">Should check "mes->use_rs64mem" as=
you do in patch #1?<o:p></o:p></span></li></ol>
<p class=3D"MsoNormal"><b><i><span style=3D"font-size:11.0pt;font-family:&q=
uot;Arial",sans-serif"><o:p> </o:p></span></i></b></p>
<p class=3D"MsoNormal"><b><i><span style=3D"font-size:11.0pt;font-family:&q=
uot;Arial",sans-serif">It doesn’t have to check here, since the =
rs64mem support will be checked in the amdgpu_mes_alloc_gang_ctx_index() as=
well.<o:p></o:p></span></i></b></p>
<p class=3D"MsoNormal"><b><i><span style=3D"font-size:11.0pt;font-family:&q=
uot;Arial",sans-serif">>> Think more about it, we may still need=
to check the
</span></i></b><b><i><span style=3D"font-size:11.0pt;font-family:"Aria=
l",sans-serif">rs64mem flag at the invocation place to make the case w=
hich disables the rs64mem work properly.</span></i></b><b><i><span style=3D=
"font-size:11.0pt;font-family:"Arial",sans-serif"><o:p></o:p></sp=
an></i></b></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt;font-family:"Ar=
ial",sans-serif"><o:p> </o:p></span></p>
<ol style=3D"margin-top:0in" start=3D"2" type=3D"1">
<li class=3D"MsoNormal" style=3D"color:black;mso-list:l2 level1 lfo3"><span=
style=3D"font-size:11.0pt">Check return error code (in oversubscription ca=
se, it may run out of index)<o:p></o:p></span></li></ol>
<p class=3D"MsoNormal"><b><i><span style=3D"font-size:11.0pt">Yeah, we add =
the error handler.
</span></i></b><span style=3D"font-size:11.0pt;color:black"><o:p></o:p></sp=
an></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt;color:black"><o:p>&n=
bsp;</o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> &=
nbsp; &nbs=
p; /* Starting with GFX11, wptr BOs must be mapped to GART for MES to deter=
mine work<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> &=
nbsp; &nbs=
p; * on unmapped queues for usermode queue oversubscription (no aggre=
gated doorbell)<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt">@@ -304,6 +308,7 @@=
static int init_user_queue(struct process_queue_manager *pqm,<o:p></o:p></=
span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> &=
nbsp; return 0;<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> <o:p></o:p></=
span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> free_gang_ctx=
_bo:<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt">+ =
amdgpu_mes_free_gang_ctx_index(&dev->adev->mes=
, (*q)->gang_ctx_array_index);<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> &=
nbsp; amdgpu_amdkfd_free_kernel_mem(dev->adev, &=
amp;(*q)->gang_ctx_bo);<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> cleanup:<o:p>=
</o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> &=
nbsp; uninit_queue(*q);<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt">@@ -386,6 +391,11 @=
@ int pqm_create_queue(struct process_queue_manager *pqm,<o:p></o:p></span>=
</p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> &=
nbsp; &nbs=
p; goto err_allocate_pqn;<o=
:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> &=
nbsp; &nbs=
p; }<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> &=
nbsp; &nbs=
p; memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE);<o:p></o:p=
></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt">+ =
/* Bind =
one MES process context slot to the whole process<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt">+ =
* =
(per device); every queue of this process reuses it.<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt">+ =
*/=
<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt">+ =
amdgpu_m=
es_alloc_proc_ctx_index(&dev->adev->mes,<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt">+ =
&nb=
sp; =
&nb=
sp; &pdd->proc_ctx_array_index);<o:p><=
/o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"><o:p> </o:p></=
span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt;color:black">Same co=
mment as above.<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt;color:black"><o:p>&n=
bsp;</o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> &=
nbsp; }<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> <o:p></o:p></=
span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"> &=
nbsp; pqn =3D kzalloc_obj(*pqn);<o:p></o:p></span><=
/p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt">--<o:p></o:p></span=
></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt">2.34.1<o:p></o:p></=
span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt"><o:p> </o:p></=
span></p>
</div>
</div>
</div>
</div>
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