Re: [PATCH 1/3] Revert "drm/amdgpu: add support for NBIO IP version 7.11.5"
Alex Deucher <[email protected]> Wed, 5 Aug 2026 11:30:38 -0400
| Newsgroups | org.freedesktop.lists.amd-gfx |
|---|---|
| Message-ID | <CADnq5_Msk6bCV_DP_Ro_4UkEYy7073NSPXtD_Eo2mAoxogkikw@mail.gmail.com> |
On Wed, Aug 5, 2026 at 5:18 AM Shubhankar Milind Sardeshpande <[email protected]> wrote: > > This reverts commit 74ab07e3290ff38b31448af7bcf2085cadbb5e1a. > > Signed-off-by: Shubhankar Milind Sardeshpande <[email protected]> Assuming patch 3 adds the new register headers, switch the order of patches 2 and 3 when you commit them. WIth that the series is: Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 - > drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 153 +++++------------- > 2 files changed, 36 insertions(+), 118 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > index a404d8aa13ee..b5a25ca2e901 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > @@ -3488,7 +3488,6 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) > break; > case IP_VERSION(6, 3, 1): > case IP_VERSION(7, 11, 4): > - case IP_VERSION(7, 11, 5): > adev->nbio.funcs = &nbif_v6_3_1_funcs; > adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; > break; > diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c > index 000516b5845a..57b0cf817afb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c > @@ -57,56 +57,12 @@ > #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10 0x0021 > #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10_BASE_IDX 2 > > -#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_nbio_7_11_5 0x8e13 > -#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_nbio_7_11_5_BASE_IDX 5 > -#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_nbio_7_11_5 0x8e14 > -#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_nbio_7_11_5_BASE_IDX 5 > -#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_nbio_7_11_5 0x8e15 > -#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_nbio_7_11_5_BASE_IDX 5 > - > -#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_nbio_7_11_5 0x012d > -#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_nbio_7_11_5_BASE_IDX 2 > -#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_nbio_7_11_5 0x012e > -#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_nbio_7_11_5_BASE_IDX 2 > - > -#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_nbio_7_11_5 0x0021 > -#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_nbio_7_11_5_BASE_IDX 2 > - > -#define regBIF_BX1_BIF_FB_EN_nbio_7_11_5 0x0100 > -#define regBIF_BX1_BIF_FB_EN_nbio_7_11_5_BASE_IDX 2 > - > -#define regBIF_BX1_INTERRUPT_CNTL_nbio_7_11_5 0x00f1 > -#define regBIF_BX1_INTERRUPT_CNTL_nbio_7_11_5_BASE_IDX 2 > -#define regBIF_BX1_INTERRUPT_CNTL2_nbio_7_11_5 0x00f2 > -#define regBIF_BX1_INTERRUPT_CNTL2_nbio_7_11_5_BASE_IDX 2 > - > -#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_nbio_7_11_5 0x0106 > -#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_nbio_7_11_5_BASE_IDX 2 > -#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_nbio_7_11_5 0x0107 > -#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_nbio_7_11_5_BASE_IDX 2 > - > -#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_nbio_7_11_5 0x00f7 > -#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_nbio_7_11_5_BASE_IDX 2 > - > -//BIF_BX1_BIF_FB_EN > -#define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT_nbio_7_11_5 0x0 > -#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT_nbio_7_11_5 0x1 > -#define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK_nbio_7_11_5 0x00000001L > -#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK_nbio_7_11_5 0x00000002L > - > static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev) > { > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) { > - WREG32_SOC15(NBIO, 0, regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_nbio_7_11_5, > - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); > - WREG32_SOC15(NBIO, 0, regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_nbio_7_11_5, > - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); > - } else { > - WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, > - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); > - WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, > - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); > - } > + WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, > + adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); > + WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, > + adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); > } > > static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev) > @@ -115,8 +71,6 @@ static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev) > > if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) > tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10); > - else if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) > - tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_nbio_7_11_5); > else > tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); > > @@ -128,21 +82,12 @@ static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev) > > static void nbif_v6_3_1_mc_access_enable(struct amdgpu_device *adev, bool enable) > { > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) { > - if (enable) > - WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN_nbio_7_11_5, > - BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK_nbio_7_11_5 | > - BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK_nbio_7_11_5); > - else > - WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN_nbio_7_11_5, 0); > - } else { > - if (enable) > - WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, > - BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | > - BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); > - else > - WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); > - } > + if (enable) > + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, > + BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | > + BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); > + else > + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); > } > > static u32 nbif_v6_3_1_get_memsize(struct amdgpu_device *adev) > @@ -155,14 +100,8 @@ static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev, > int doorbell_index, > int doorbell_size) > { > - u32 doorbell_range; > if (instance == 0) { > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) > - doorbell_range = RREG32_SOC15(NBIO, 0, > - regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10); > - else > - doorbell_range = RREG32_SOC15(NBIO, 0, > - regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL); > + u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL); > > if (use_doorbell) { > doorbell_range = REG_SET_FIELD(doorbell_range, > @@ -191,10 +130,12 @@ static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev, > S2A_DOORBELL_PORT2_RANGE_SIZE, > 0); > > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) > - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10, doorbell_range); > + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) > + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10, > + doorbell_range); > else > - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); > + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, > + doorbell_range); > } > } > > @@ -239,15 +180,15 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, > S2A_DOORBELL_PORT4_RANGE_SIZE, > 0); > > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) > - WREG32_SOC15(NBIO, 0, > - regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, > - doorbell_range); > - else > + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { > + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, > + doorbell_range); > + } else { > if (instance) > WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); > else > WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); > + } > } > > static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev, > @@ -299,7 +240,7 @@ static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev, > > static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev) > { > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) { > + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { > WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10, 0x30000007); > WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10, 0x3000000d); > } else { > @@ -341,13 +282,7 @@ nbif_v6_3_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, > static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev, > bool use_doorbell, int doorbell_index) > { > - u32 ih_doorbell_range; > - > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) > - ih_doorbell_range = RREG32_SOC15(NBIO, 0, > - regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10); > - else > - ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL); > + u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL); > > if (use_doorbell) { > ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, > @@ -376,11 +311,12 @@ static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev, > S2A_DOORBELL_PORT1_RANGE_SIZE, > 0); > > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) > + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) > WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10, > - ih_doorbell_range); > + ih_doorbell_range); > else > - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); > + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, > + ih_doorbell_range); > } > > static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev) > @@ -388,13 +324,9 @@ static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev) > u32 interrupt_cntl; > > /* setup interrupt control */ > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) > - WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2_nbio_7_11_5, > - adev->dummy_page_addr >> 8); > - else > - WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); > + WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); > > - interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL_nbio_7_11_5); > + interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); > /* > * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi > * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN > @@ -406,10 +338,7 @@ static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev) > interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, > IH_REQ_NONSNOOP_EN, 0); > > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) > - WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL_nbio_7_11_5, interrupt_cntl); > - else > - WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); > + WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); > } > > static void > @@ -432,23 +361,17 @@ nbif_v6_3_1_get_clockgating_state(struct amdgpu_device *adev, > > static u32 nbif_v6_3_1_get_hdp_flush_req_offset(struct amdgpu_device *adev) > { > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) > - return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_nbio_7_11_5); > - else > - return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); > + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); > } > > static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) > { > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) > - return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_nbio_7_11_5); > - else > - return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); > + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); > } > > static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev) > { > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) > + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) > return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX); > else > return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); > @@ -456,7 +379,7 @@ static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev) > > static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev) > { > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) > + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) > return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA); > else > return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); > @@ -626,12 +549,8 @@ static void nbif_v6_3_1_set_reg_remap(struct amdgpu_device *adev) > adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; > adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; > } else { > - if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) > - adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, > - regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_nbio_7_11_5) << 2; > - else > - adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, > - regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; > + adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, > + regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; > adev->rmmio_remap.bus_addr = 0; > } > } > -- > 2.43.0 >