[PATCH 040/109] drm/amd/ras: Support retrieving bad page info from mp1_v15_0

Alex Deucher <[email protected]>
Newsgroups org.freedesktop.lists.amd-gfx
Message-ID <[email protected]> 
From: YiPeng Chai <[email protected]>

Support retrieving bad page info from mp1_v15_0.

Signed-off-by: YiPeng Chai <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
---
 drivers/gpu/drm/amd/ras/core/Makefile         |   1 +
 drivers/gpu/drm/amd/ras/core/ras.h            |   2 +-
 drivers/gpu/drm/amd/ras/core/ras_mp1.c        |   4 +-
 drivers/gpu/drm/amd/ras/core/ras_mp1.h        |  14 ++
 drivers/gpu/drm/amd/ras/core/ras_mp1_v15_0.c  | 129 ++++++++++++++++++
 drivers/gpu/drm/amd/ras/core/ras_mp1_v15_0.h  |  30 ++++
 drivers/gpu/drm/amd/ras/ras_mgr/Makefile      |   1 +
 .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c  |   3 +-
 .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c  |  70 ++++++++++
 .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.h  |  30 ++++
 10 files changed, 280 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/ras/core/ras_mp1_v15_0.c
 create mode 100644 drivers/gpu/drm/amd/ras/core/ras_mp1_v15_0.h
 create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c
 create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.h

diff --git a/drivers/gpu/drm/amd/ras/core/Makefile b/drivers/gpu/drm/amd/ras/core/Makefile
index 2dfb1f96b072f..1f4d6d642a73a 100644
--- a/drivers/gpu/drm/amd/ras/core/Makefile
+++ b/drivers/gpu/drm/amd/ras/core/Makefile
@@ -22,6 +22,7 @@
 RAS_CORE_FILES = core.o \
 			ras_mp1.o \
 			ras_mp1_v13_0.o \
+			ras_mp1_v15_0.o \
 			aca.o  \
 			aca_v1_0.o \
 			ras_aca_v5_0.o \
diff --git a/drivers/gpu/drm/amd/ras/core/ras.h b/drivers/gpu/drm/amd/ras/core/ras.h
index 47cc934520448..10fa7068fc7a4 100644
--- a/drivers/gpu/drm/amd/ras/core/ras.h
+++ b/drivers/gpu/drm/amd/ras/core/ras.h
@@ -200,7 +200,7 @@ struct ras_mp1_sys_func {
 	int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core,
 			u32 msg, u32 idx, u32 reg_idx, u64 *val);
 	int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core,
-			enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg);
+			u32 msg_id, uint32_t param, uint32_t *read_arg);
 	int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core,
 			uint64_t *enabled_mask);
 	int (*mp1_set_debug_mode)(struct ras_core_context *ras_core, bool enable);
diff --git a/drivers/gpu/drm/amd/ras/core/ras_mp1.c b/drivers/gpu/drm/amd/ras/core/ras_mp1.c
index eccd6f16c35a7..7a2a6da26ae38 100644
--- a/drivers/gpu/drm/amd/ras/core/ras_mp1.c
+++ b/drivers/gpu/drm/amd/ras/core/ras_mp1.c
@@ -25,6 +25,7 @@
 #include "ras.h"
 #include "ras_mp1.h"
 #include "ras_mp1_v13_0.h"
+#include "ras_mp1_v15_0.h"
 
 static const struct ras_mp1_ip_func *ras_mp1_get_ip_funcs(
 				struct ras_core_context *ras_core, uint32_t ip_version)
@@ -35,8 +36,7 @@ static const struct ras_mp1_ip_func *ras_mp1_get_ip_funcs(
 	case IP_VERSION(13, 0, 12):
 		return &mp1_ras_func_v13_0;
 	case IP_VERSION(15, 0, 8):
-		//TBD for dGPU
-		break;
+		return &mp1_ras_func_v15_0;
 	default:
 		RAS_DEV_ERR(ras_core->dev,
 			"MP1 ip version(0x%x) is not supported!\n", ip_version);
diff --git a/drivers/gpu/drm/amd/ras/core/ras_mp1.h b/drivers/gpu/drm/amd/ras/core/ras_mp1.h
index a00eb8117885b..3b3d4cab1d0c9 100644
--- a/drivers/gpu/drm/amd/ras/core/ras_mp1.h
+++ b/drivers/gpu/drm/amd/ras/core/ras_mp1.h
@@ -25,6 +25,20 @@
 #define __RAS_MP1_H__
 #include "ras.h"
 
+enum ras_mp1_msg_id {
+	RAS_MP1_MSG_GetRasTableVersion,
+	RAS_MP1_MSG_GetRmaStatus,
+	RAS_MP1_MSG_GetBadPageCount,
+	RAS_MP1_MSG_GetBadPageMcaAddr,
+	RAS_MP1_MSG_GetBadPagePaAddr,
+	RAS_MP1_MSG_SetTimestamp,
+	RAS_MP1_MSG_GetTimestamp,
+	RAS_MP1_MSG_GetRasPolicy,
+	RAS_MP1_MSG_GetBadPageIpId,
+	RAS_MP1_MSG_EraseRasTable,
+	RAS_MP1_MSG_MAX
+};
+
 struct eeprom_err_record {
 	u32 timestamp;
 
diff --git a/drivers/gpu/drm/amd/ras/core/ras_mp1_v15_0.c b/drivers/gpu/drm/amd/ras/core/ras_mp1_v15_0.c
new file mode 100644
index 0000000000000..2cd0f266b5855
--- /dev/null
+++ b/drivers/gpu/drm/amd/ras/core/ras_mp1_v15_0.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "ras.h"
+#include "ras_mp1.h"
+#include "core_status.h"
+#include "ras_mp1_v13_0.h"
+
+#define MSG_DATA_LOW32(idx)   (idx | (0x1 << 16))
+#define MSG_DATA_HIGH32(idx)  (idx | (0x2 << 16))
+
+static int __send_mp1_msg(struct ras_core_context *ras_core,
+		enum ras_mp1_msg_id msg_id, u32 input, u32 *output)
+{
+	if (msg_id >= RAS_MP1_MSG_MAX)
+		return -EINVAL;
+
+	return ras_core->ras_mp1.sys_func->mp1_send_eeprom_msg(ras_core,
+				msg_id, input, output);
+}
+
+static int ras_mp1_v15_get_table_version(struct ras_core_context *ras_core,
+				     u32 *table_ver)
+{
+	return __send_mp1_msg(ras_core, RAS_MP1_MSG_GetRasTableVersion,
+			0, table_ver);
+}
+
+static bool ras_mp1_v15_rma_detected(struct ras_core_context *ras_core)
+{
+	u32 rma = 0;
+
+	if (__send_mp1_msg(ras_core, RAS_MP1_MSG_GetRmaStatus, 0, &rma))
+		return false;
+
+	return rma;
+}
+
+static int ras_mp1_v15_set_timestamp(struct ras_core_context *ras_core,
+			u32 timestamp)
+{
+	if (!timestamp)
+		return -EINVAL;
+
+	return __send_mp1_msg(ras_core, RAS_MP1_MSG_SetTimestamp, timestamp, NULL);
+}
+
+static int ras_mp1_v15_reset_ras_table(struct ras_core_context *ras_core,
+				   u32 *result)
+{
+	if (!result)
+		return -EINVAL;
+
+	return __send_mp1_msg(ras_core, RAS_MP1_MSG_EraseRasTable, 0, result);
+}
+
+static int ras_mp1_v15_get_record_count(struct ras_core_context *ras_core,
+				u32 *count)
+{
+	if (!count)
+		return -EINVAL;
+
+	*count = 0;
+
+	return __send_mp1_msg(ras_core, RAS_MP1_MSG_GetBadPageCount, 0, count);
+}
+
+static int ras_mp1_v15_get_record(struct ras_core_context *ras_core,
+			u32 idx, struct eeprom_err_record *rec)
+{
+	int ret;
+
+	if (!rec)
+		return 0;
+
+	ret = __send_mp1_msg(ras_core, RAS_MP1_MSG_GetTimestamp,
+			idx, &rec->timestamp);
+	if (ret)
+		return ret;
+
+	ret = __send_mp1_msg(ras_core, RAS_MP1_MSG_GetBadPageMcaAddr,
+			MSG_DATA_LOW32(idx), &rec->mca_addr_low);
+	if (ret)
+		return ret;
+
+	ret = __send_mp1_msg(ras_core, RAS_MP1_MSG_GetBadPageMcaAddr,
+			MSG_DATA_HIGH32(idx), &rec->mca_addr_high);
+	if (ret)
+		return ret;
+
+	ret = __send_mp1_msg(ras_core, RAS_MP1_MSG_GetBadPageIpId,
+			MSG_DATA_LOW32(idx), &rec->ipid_low);
+	if (ret)
+		return ret;
+
+	ret = __send_mp1_msg(ras_core, RAS_MP1_MSG_GetBadPageIpId,
+			MSG_DATA_HIGH32(idx), &rec->ipid_high);
+
+	return ret;
+}
+
+const struct ras_mp1_ip_func mp1_ras_func_v15_0 = {
+	.get_table_version = ras_mp1_v15_get_table_version,
+	.rma_detected = ras_mp1_v15_rma_detected,
+	.set_timestamp = ras_mp1_v15_set_timestamp,
+	.reset_ras_table = ras_mp1_v15_reset_ras_table,
+	.get_record_count = ras_mp1_v15_get_record_count,
+	.get_record = ras_mp1_v15_get_record,
+};
diff --git a/drivers/gpu/drm/amd/ras/core/ras_mp1_v15_0.h b/drivers/gpu/drm/amd/ras/core/ras_mp1_v15_0.h
new file mode 100644
index 0000000000000..c93b40a604c1a
--- /dev/null
+++ b/drivers/gpu/drm/amd/ras/core/ras_mp1_v15_0.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __RAS_MP1_V15_0_H__
+#define __RAS_MP1_V15_0_H__
+#include "ras_mp1.h"
+
+extern const struct ras_mp1_ip_func mp1_ras_func_v15_0;
+
+#endif
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/Makefile b/drivers/gpu/drm/amd/ras/ras_mgr/Makefile
index 70649c49d1ff6..3df2a290f67b1 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/Makefile
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/Makefile
@@ -22,6 +22,7 @@ RAS_MGR_FILES = amdgpu_ras_sys.o  \
 		amdgpu_ras_mgr.o \
 		amdgpu_ras_eeprom_i2c.o \
 		amdgpu_ras_mp1_v13_0.o \
+		amdgpu_ras_mp1.o \
 		amdgpu_ras_cmd.o \
 		amdgpu_virt_ras_cmd.o \
 		amdgpu_ras_process.o \
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
index 030edfebd0b78..c71bd447d1b2c 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
@@ -31,6 +31,7 @@
 #include "amdgpu_ras_process.h"
 #include "amdgpu_ras_eeprom_i2c.h"
 #include "amdgpu_ras_mp1_v13_0.h"
+#include "amdgpu_ras_mp1.h"
 #include "amdgpu_ras_nbio_v7_9.h"
 #include "amdgpu_ras_mce.h"
 
@@ -212,7 +213,7 @@ static int amdgpu_ras_mgr_init_mp1_config(struct amdgpu_device *adev,
 		mp1_cfg->mp1_sys_fn = &amdgpu_ras_mp1_sys_func_v13_0;
 		break;
 	case IP_VERSION(15, 0, 8):
-		//TBD for dGPU
+		mp1_cfg->mp1_sys_fn = &amdgpu_ras_mp1_sys_func;
 		break;
 	default:
 		RAS_DEV_ERR(adev,
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c
new file mode 100644
index 0000000000000..b2d9148a36f99
--- /dev/null
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu_smu.h"
+#include "amdgpu_reset.h"
+#include "ras.h"
+
+static const enum smu_message_type ras_smu_msg_maps[RAS_MP1_MSG_MAX] = {
+	[RAS_MP1_MSG_GetRasTableVersion] = SMU_MSG_GetRASTableVersion,
+	[RAS_MP1_MSG_GetBadPageCount] = SMU_MSG_GetBadPageCount,
+	[RAS_MP1_MSG_GetBadPageMcaAddr] = SMU_MSG_GetBadPageMcaAddr,
+	[RAS_MP1_MSG_SetTimestamp] = SMU_MSG_SetTimestamp,
+	[RAS_MP1_MSG_GetTimestamp] = SMU_MSG_GetTimestamp,
+	[RAS_MP1_MSG_GetBadPageIpId] = SMU_MSG_GetBadPageIpid,
+	[RAS_MP1_MSG_EraseRasTable] = SMU_MSG_EraseRasTable,
+};
+
+static enum smu_message_type
+	__get_ras_smu_msg(struct ras_core_context *ras_core, u32 msg_id)
+{
+	if (msg_id >= RAS_MP1_MSG_MAX)
+		return 0;
+
+	return ras_smu_msg_maps[msg_id];
+}
+
+static int amdgpu_ras_send_mp1_msg(struct ras_core_context *ras_core,
+			u32 msg_id, uint32_t param, uint32_t *read_arg)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
+	enum smu_message_type smu_msg;
+	int ret = 0;
+
+	smu_msg = __get_ras_smu_msg(ras_core, msg_id);
+	if (!smu_msg)
+		return -EOPNOTSUPP;
+
+	if (down_read_trylock(&adev->reset_domain->sem)) {
+		ret = amdgpu_smu_ras_send_msg(adev, smu_msg, param, read_arg);
+		up_read(&adev->reset_domain->sem);
+	} else {
+		ret = -RAS_CORE_GPU_IN_MODE1_RESET;
+	}
+
+	return ret;
+}
+
+const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func = {
+	.mp1_send_eeprom_msg = amdgpu_ras_send_mp1_msg,
+};
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.h
new file mode 100644
index 0000000000000..fa7231b03ccdf
--- /dev/null
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __AMDGPU_RAS_MP1_H__
+#define __AMDGPU_RAS_MP1_H__
+#include "ras.h"
+
+extern const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func;
+
+#endif
-- 
2.55.0
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