[PATCH 101/109] drm/amd/ras: preserve CPU MCE context in the log ring

From: Xiang Liu <[email protected]>

Processor CPER generation needs the APIC ID and machine-check bank
number in addition to the ACA register values. Logging the full internal
ACA bank also exceeds the stable fixed-size log body representation.

Carry the APIC ID and bank number with incoming ACA banks and store CPU
MCE events in a compact 128-byte log context for later CPER encoding.

Signed-off-by: Xiang Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
---
 drivers/gpu/drm/amd/ras/core/aca.h      |  2 ++
 drivers/gpu/drm/amd/ras/core/log_ring.h | 21 ++++++++++++++++++++-
 drivers/gpu/drm/amd/ras/core/ras_mce.c  |  9 +++++++--
 3 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/ras/core/aca.h b/drivers/gpu/drm/amd/ras/core/aca.h
index 52acf19fac11a..759119bed870c 100644
--- a/drivers/gpu/drm/amd/ras/core/aca.h
+++ b/drivers/gpu/drm/amd/ras/core/aca.h
@@ -54,6 +54,8 @@ struct aca_bank_reg {
 	uint64_t timestamp;
 	u32 bank_type;
 	u32 ecc_type;
+	u32 apic_id;
+	u32 bank;
 	u64 seq_no;
 	u64 regs[ACA_REG_MAX_COUNT];
 };
diff --git a/drivers/gpu/drm/amd/ras/core/log_ring.h b/drivers/gpu/drm/amd/ras/core/log_ring.h
index ed68664bf3c68..2d8e40c971062 100644
--- a/drivers/gpu/drm/amd/ras/core/log_ring.h
+++ b/drivers/gpu/drm/amd/ras/core/log_ring.h
@@ -48,16 +48,35 @@ struct ras_aca_reg {
 	uint64_t regs[ACA_REG_MAX_COUNT];
 };
 
+struct ras_cpu_mce {
+	u64 regs[ACA_REG_MAX_COUNT - 1];
+	u32 apic_id;
+	u16 bank;
+	u16 reserved;
+};
+
+#define RAS_CPER_BOOT_RAW_DATA_SIZE	80
+#define RAS_BOOT_CTX_VALID_APIC_ID	BIT(0)
+
 struct ras_boot_err_ctx {
 	u8 section_type[16];
 	u32 error_severity;
 	u16 reg_ctx_type;
 	u16 reg_arr_size;
-	u64 regs[CPER_OAM_MAX_COUNT];
+	u32 msr_addr;
+	u16 raw_data_size;
+	u16 flags;
+	u64 apic_id;
+	u64 mm_reg_addr;
+	union {
+		u64 regs[CPER_OAM_MAX_COUNT];
+		u8 raw_data[RAS_CPER_BOOT_RAW_DATA_SIZE];
+	};
 };
 
 union ras_log_body {
 	struct ras_aca_reg aca_reg;
+	struct ras_cpu_mce cpu_mce;
 	struct ras_boot_err_ctx boot_err_ctx;
 };
 
diff --git a/drivers/gpu/drm/amd/ras/core/ras_mce.c b/drivers/gpu/drm/amd/ras/core/ras_mce.c
index 018429e397979..71281917b132a 100644
--- a/drivers/gpu/drm/amd/ras/core/ras_mce.c
+++ b/drivers/gpu/drm/amd/ras/core/ras_mce.c
@@ -70,7 +70,7 @@ static int ras_mce_add_gpu_bank(struct ras_core_context *ras_core,
 	ret = kfifo_in_spinlocked(&mce->mce_fifo,
 			aca_bank, sizeof(*aca_bank), &mce->mce_fifo_lock);
 	if (ret)
-		ras_process_add_interrupt_req(ras_core, NULL, true);
+		ras_process_add_interrupt_req(ras_core, NULL, false);
 
 	return ret ? 0 : -ENOSPC;
 }
@@ -78,9 +78,14 @@ static int ras_mce_add_gpu_bank(struct ras_core_context *ras_core,
 static int ras_mce_log_cpu_bank(struct ras_core_context *ras_core,
 			struct aca_bank_reg *aca_bank)
 {
+	struct ras_cpu_mce cpu_mce = {
+		.apic_id = aca_bank->apic_id,
+		.bank = aca_bank->bank,
+	};
 
+	memcpy(cpu_mce.regs, aca_bank->regs, sizeof(cpu_mce.regs));
 	ras_log_ring_add_log_event(ras_core,
-		RAS_LOG_EVENT_CPU_RAS, aca_bank, sizeof(*aca_bank), NULL);
+		RAS_LOG_EVENT_CPU_RAS, &cpu_mce, sizeof(cpu_mce), NULL);
 
 	return 0;
 }
-- 
2.55.0