Re: [PATCH] drm/amdgpu/userq: fix struct drm_amdgpu_info_device padding for 32bit compile

AMD General

Hi Alex,

In 32bit mesa, I did not get the correct userq_ip_mask value.
I checked for variable alignment and tcc_disabled_mask was not on 8 byte alignment. This patch fixes it.

Can you please tell how it would break UAPI. What did I miss.

Thank you,
Yogesh

________________________________
From: Alex Deucher <[email protected]>
Sent: Thursday, August 20, 2026 7:23 PM
To: Mohan Marimuthu, Yogesh <[email protected]>
Cc: [email protected] <[email protected]>; Deucher, Alexander <[email protected]>; Koenig, Christian <[email protected]>; Khatri, Sunil <[email protected]>
Subject: Re: [PATCH] drm/amdgpu/userq: fix struct drm_amdgpu_info_device padding for 32bit compile

On Thu, Aug 20, 2026 at 12:55 AM Yogesh Mohan Marimuthu
<[email protected]> wrote:
>
> need to pad before __u64 tcc_disabled_mask variable.
>
> Signed-off-by: Yogesh Mohan Marimuthu <[email protected]>

This will break UAPI.

Alex

> ---
>  include/uapi/drm/amdgpu_drm.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 0a113529b..5beef3eaa 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -1517,6 +1517,7 @@ struct drm_amdgpu_info_device {
>         __u64 high_va_max;
>         /* gfx10 pa_sc_tile_steering_override */
>         __u32 pa_sc_tile_steering_override;
> +       __u32 pad;
>         /* disabled TCCs */
>         __u64 tcc_disabled_mask;
>         __u64 min_engine_clock;
> @@ -1541,7 +1542,6 @@ struct drm_amdgpu_info_device {
>         __u32 csa_alignment;
>         /* Userq IP mask (1 << AMDGPU_HW_IP_*) */
>         __u32 userq_ip_mask;
> -       __u32 pad;
>  };
>
>  struct drm_amdgpu_info_hw_ip {
> --
> 2.43.0
>